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VLDB 2026 Research / reviewers in the wild / expert

M. Gall

dblp:10/1170 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1997
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 87% Memory systems · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › circuit modeling
circuit performance modeling		 0.011997
Process variation effects on circuit performance: TCAD simulation of 256-Mbit technology [DRAMs] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997
Electronic design automation › technology computer-aided design
process simulation		 0.011997
Process variation effects on circuit performance: TCAD simulation of 256-Mbit technology [DRAMs] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997
Memory systems
DRAM		 0.011997
Process variation effects on circuit performance: TCAD simulation of 256-Mbit technology [DRAMs] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997

Methods — techniques the papers use, named apart from their topics

device calibration · 0.0TCAD simulation · 0.0
YearPublicationVenuePosition
1997 Process variation effects on circuit performance: TCAD simulation of 256-Mbit technology [DRAMs]
abstract
This paper describes the first study of the complete sequence from process simulation to circuit performance and the corresponding sensitivities for 0.25-/spl mu/m technology. This is made possible by a combination of physically based process models and a systematic calibration involving SIMS, one-dimensional (1-D), and two-dimensional (2-D) device characteristics. Simulated nFET and pFET characteristics match hardware (HW) within 5-10% for both long-channel and nominal length devices. Simulated ring-oscillator performance is in good agreement with HW data. Sensitivities of device characteristics and the inverter gate delay to process variations (within 10%) are quantified. These investigations establish the correlation between process variations and circuit performance.
C. S. Murthy, M. Gall
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2