This correspondence deals with the fault-tolerant realization of a sequential machine using error-correcting (n,k) linear codes. Earlier works in the same area confine their attention to modified Reed-Muller Code and perfect Hamming Code and achieve the realization using a number of majority logic gates, which makes the entire realization quite complex. The realization discussed in this paper needs a smaller number of circuit components with less complexity.

Given a synchronous sequential machine M, this correspondence deals with the fault-tolerant realization M of M and also its fail-safe realization M on the assumption that the faults that can occur to the circuitry of M or M are of permanent stuck-at type and the total number of faults can be at most some preset positive integer r. First, the realization of M or M is derived for r = 1 and then the same idea is extended to have the realization for any arbitrary r. It has been shown that the realization of M is such that it is also able to tolerate faults of nonpermanent nature.

The necessary and sufficient conditions for the linear realizability of a sequential machine are stated. The discussion considers the state transition and output functions separately and thus machines with nonlinear output function can also be tested for linearity of the state transition function. It then goes on to determine the characterizing matrices and corresponding secondary state assignment when such realization exists. The method can be applied to both permutation and nonpermutation machines.