Previously proposed error detection algorithms for the residue number system require a complete recombination. A weighted approximation via the Chinese remainder theorem is shown to be sufficient to detect 100% of single errors. This makes real-time single-error diagnosis possible, which involves up to N+2 iterations of detection (N is the number of nonredundant channels). One approach uses a scaled range of L+1+log/sub 2/ (N+1) bits for detection in contrast with full decoding of approximately=L(N+1) bits, where L is the number of bits in the largest modulus. A second method forms a redundant residue number representation of the overflow multiplier A(x), although A(x) does not need to be carried through processing operations. This permits real-time single-error diagnosis and correction with a parallel array of approximately=(N+2)/sup 2/ tables.>

Several VLSI architectures for performing exponentiation in GF(2/sup m/) are presented. Two approaches to the architecture design are taken. In the first, all intermediate products of the exponentiation are computed in a sequential fashion to minimize the silicon area. In the second approach, all values of raised to the 2/sup ei/ power, O>

This paper describes the theory, design, and testing of a Viterbi processor for a digital communication system with intersymbol interference over fading time-dispersive channels. The requirement is to implement the Viterbi algorithm for a channel memory of 9 baud at a data rate of 2400 bits/s. The processor is partitioned into three subprocessors corresponding to the correlation, state metric evaluation, and state decision-making operations. For prototype evaluation, each subprocessor is being implemented as a separate chip using4-5 \mum CMOS technology. The architecture, circuit design, and subsystem characterization of the correlator chip are described in some detail. The chip is required to evaluate 1024 state transition metrics in each baud interval (about 400 ns) using a pipeline architecture. Simulation and initial test results verify the correct operation of the chip with an adequate-speed safety margin. The theory of operation and architecture of the state metric chip are described. With off-chip memory for state metric storage, the state transition metrics from the correlator chip are used to determine the winning (optimal) path in the Viterbi trellis and to calculate the corresponding 16-bit state metric for each baud interval. Implementation of the third chip which is required to make a state decision regarding the bit sequence sent is presently being investigated.

Multiplication in the finite fieldGF(2^{m}) has particular computational advantages in data encryption systems. This paper presents a new algorithm for performing fast multiplication inGF(2^{m}), which isO(m)in computation time and implementation area. The bit-slice architecture of a serial-in-serial-out modulo multiplier is described and the circuit details given. The design is highly regular, modular, and well-suited for VLSI implementation. The resulting multiplier will have application in algorithms based on arithmetic in large finite fields of characteristic 2, and which require high throughput.