Deep neural network (DNN) inference relies increasingly on specialized hardware for high computational efficiency. This work introduces a field-programmable gate array (FPGA)-based dynamically configurable accelerator featuring systolic arrays (SAs), high-bandwidth memory (HBM), and UltraRAMs. We present two processing unit (PU) configurations with different computing capabilities using the same interfaces and peripheral blocks. By instantiating multiple PUs and employing a heuristic weight transfer schedule, the architecture achieves notable throughput efficiency over prior works. Moreover, we outline how the architecture can be extended to emulate analog in-memory computing (AIMC) devices to aid next-generation heterogeneous AIMC chip designs and investigate device-level noise behavior. Overall, this brief presents a versatile DNN inference acceleration architecture adaptable to various models and future FPGA designs.

In-memory computing is an emerging non-von Neumann computing paradigm where certain computational tasks are performed in memory by exploiting the physical attributes of the memory devices. Memristive devices such as phase-change memory (PCM), where information is stored in terms of their conductance levels, are especially well suited for in-memory computing. In particular, memristive devices, when organized in a crossbar configuration can be used to perform matrix-vector multiply operations by exploiting Kirchhoff's circuit laws. To explore the feasibility of such in-memory computing cores in applications such as deep learning as well as for system-level architectural exploration, it is highly desirable to develop an accurate hardware emulator that captures the key physical attributes of the memristive devices. Here, we present one such emulator for PCM and experimentally validate it using measurements from a PCM prototype chip. Moreover, we present an application of the emulator for neural network inference where our emulator can capture the conductance evolution of approximately 400,000 PCM devices remarkably well.

Phase-change memory (PCM) is a technology that can be exploited not only on next-generation storage systems but also on new computing paradigms, like the in-memory computing approach. For experimenting with different characteristics of PCM technology in large-scale PCM-based circuits and devices, we developed an accurate and precise hardware PCM emulator, which can model PCM circuits at the cell, array and matrix level. In this work, we present details of the PCM emulator, its architecture and experimental results on its use for implementing basic linear algebra functions.

A modular and versatile FPGA-based platform, designed for accurate emulation of multiple NAND Flash channels is presented in this work. The emulator is based on an expandable and reconfigurable hardware-software architecture that can be used for developing and testing of new NAND Flash controllers and for analyzing the behavior of existing NAND Flash controllers. The proposed emulator is based on PCIe-based FPGA boards attached to a high-end Xeon server, supports standard memory interfaces, responds in proper time and has the capability to emulate memory space in the range of a few hundred GBs per channel. The emulator has been prototyped and tested and experimental results demonstrate that all timing requirements are satisfied under maximum read/write workloads.

Novel forms of nonvolatile memory, such as phase-change memory (PCM), promise low latency and small granularity of read and write access at high storage density. They also feature very high endurance. These characteristics make them highly desirable for emerging high-capacity (hybrid) memory applications such as in-memory databases and in-memory processing. In this work, we present the architecture, implementation and experimental performance results of an FPGA-based PCM memory controller for OpenPOWER servers. The memory controller leverages the Coherent Accelerator Processor Interface (CAPI) of the POWER processor in order to offer low-latency access to the CPU memory space. In addition, the memory controller implements an efficient management protocol that supports a dynamic size of pending read and write requests in order to offer high bandwidth under mixed-type workloads. We describe the architecture and implementation details of the memory controller and we demonstrate its performance using a prototype platform based on different types of OpenPOWER servers equipped with CAPI-enabled FPGA cards. The developed PCM controller is evaluated in terms of sustained data rates (MBps) and access latency (us). Experimental results are based on legacy commercial 90nm PCM chips as well as on accurate HW emulation of next generation PCM chips.

This work presents a versatile and flexible FPGA-based platform, designed for accurate emulation of the aging effect of non-volatile memories. The emulator is based on a reconfigurable hardware-software architecture which enables the accurate representation of various non-volatile memory technologies, like NAND Flash and PCM. The proposed architecture can be used for emulating memories at the cell, chip and system level, while the proposed hardware platform can be used as a valuable tool for the development and evaluation of memory-related algorithms and techniques. In this paper, we analyze the architecture of the non-volatile memory emulator, focusing mainly on the NAND Flash case, we present details about its internal functionality and, using experimental results, we demonstrate the high accuracy achieved when it is used to emulate a specific NAND Flash chip.

Solid-state drives use non-volatile memories for storing and retrieving information in the form of sectors and/or pages and demonstrate better performance than hard disks. In many cases, the maximum IO performance of the used memory technology is not achieved due to limitations imposed by the software device driver that interfaces the storage card with the hosts's operating system. Today's computing machines with conventional operating systems have been developed based on the performance characteristics of hard disk drives. In this work, we present the prototype of a new block device driver with a flexible host-device interface suitable for PCIe-based solid-state drives. The block device driver is compatible with the standard software dataflow of a Linux-based OS, and at the same time exploits the operational features of such devices to provide improved performance. Experimental results that demonstrate how the system performance is affected by decisions on the device driver's functionality are presented along with the used testing methodology.

This paper presents the design and implementation of a baseband demodulator for DVB-S2 satellite receivers. In order to meet the requirements of different complex and multidomain signal processing stages of the DVB-S2 baseband signal-flow, the presented architecture is based on efficient fixed-point implementation of the various demodulation algorithms and on the use of a dynamic time-sharing scheduler for the various DSP software tasks. The prototyping of the demodulator and its verification in the design of a complete digital DVB-S2 satellite receiver using a versatile testbed is also presented.

High density probe-based storage devices use multiple, simultaneously accessed parallel channels for achieving high I/O data rates. This paper presents an analytical methodology for evaluating the performance of coding and interleaving schemes in such devices, when they are affected by burst errors. Markov processes are used to describe the burstiness of errors due to external disturbances and analytical formulas are provided to estimate the system reliability for various system parameters. Using this approach, the most appropriate system configuration, in terms of number of Reed-Solomon codewords, interleaving depth and coding rate can be determined for a given system reliability and storage efficiency.

This letter presents a new bit-loading algorithm for discrete multitone systems that converges faster to the same bit allocation as the optimal discrete bit-filling and bit-removal methods. The algorithm exploits the differences between the subchannel gain-to-noise ratios in order to determine an initial bit allocation and then performs a multiple-bits loading procedure for achieving the requested target rate. Numerical results using asymmetric digital subscriber test loops demonstrate the computational efficiency of the proposed algorithm.

100BASE-T has enhanced the performance of Ethernet networks from 10 to 100 Mbps. However, an Ethernet network under high offered load can produce unpredictable and excessive packet delays due to the capture effect introduced by the binary exponential backoff (BEB) algorithm. A solution that efficiently overcomes this problem is the PACE algorithm. This paper presents a performance analysis of several schemes of an algorithm based on PACE technology. We developed a mathematical model of the system and we used the equilibrium point analysis (EPA) technique in order to analyze the above model. It is shown that the proposed schemes improve the performance of the network both in terms of throughput and average packet delay.

The IEEE802.11 standard for wireless local area networks allows the coexistence of asynchronous and time-bounded transmissions using the distributed coordination function (DCF) and point coordination function (PCF) modes of operation. We present the integration of packetized voice and data traffic over an IEEE802.11 basic service set (BSS) network and we analyze its performance in terms of maximum number of supported conversations and minimum bandwidth available for data transfers. The use of echo cancellation is considered and its effect on network performance is also analyzed.

This paper presents a new polling scheme that can be used at the access point of an IEEE 802.11 wireless network as part of the point coordination function, in order to provide guaranteed QoS support of voice traffic. The so called cyclic shift polling scheme, along with the use of silence detection at the mobile terminals, increases the supported number of calls as a function of the overall rate of dropped voice packets and the point coordination function repetition interval. The advantages of utilizing this polling scheme are demonstrated by using the voice delay and voice jitter distributions. The delay and jitter distributions confirm that the voice packet delay introduced by the wireless network can be less than 25 ms even in the case of stations of different wireless networks when the IEEE 802.11 LANs are interconnected via an ATM infrastructure.

This paper presents the coding and timing recovery issues of an interface for high-speed cell-based communication networks. The synchronization technique used in this interface is based on the functionality resulting from combining functions of Fibre Channel with the basic features of pure ATM. The line coding properties, along with a pseudo-framing structure, are used to simplify the cell delineation process, thus resulting in lower hardware complexity than existing ATM interfaces, and implementability at high transmission rates. The paper describes also the architecture of a prototyped interface and its implementation using commercially available and custom ICs at 1 Gbps.

This paper describes the architecture of a software tool for CASE products evaluation. The tool is based on the ISO software product quality evaluation process model, which has been extended using fuzzy sets theory for achieving more reliable results. The evaluation tool can determine which CASE product is the most appropriate for a specific application and can generate the initial models of the system for further processing by the selected CASE tool. This is achieved by using an inference process based on fuzzy rules for mapping user's specifications into software metrics. Fuzzy sets are employed to express concepts such as the strength of each criterion involved in the evaluation, its relative importance, etc. The evaluation tool architecture is modular while the fuzzy rules, the definition of the used fuzzy sets and the tool database can be easily modified by the user for accurately describing his requirements.

This paper presents the basic components and configurations of a real-time test-bed developed for prototyping cell-based communication systems. Although it was initially developed for demonstrating the effectiveness of compression and adaptation techniques in 3DTV transmission over B-ISDN, the test-bed can also be used for measuring the performance of various services and applications over B-ISDN and other cell-based networks. The hardware has been based mainly on FPGAs, allowing the implementation of various communication functions following either the CCITT recommendations or proprietary access protocols.>

The design and implementation of a high-speed access mechanism for a fiber-optic multiservice LAN is presented. The handling of stream-type and burst-type communications is accomplished through the use of a distributed hybrid switching protocol that uses an asynchronous dynamic time-division-multiplexing technique. The network comprises a write channel in which each network node transmits and a read channel where the transmitted information is duplicated and thus received by the network nodes. In parallel with the write channel, a sense channel is responsible for detecting the right of access for the node. The protocol provides bounded delay for the packet-switched traffic and small buffering memory for the circuit-switched traffic, which together with the network bit rate and the node processing time and capacity set the network efficiency. Experimental results are presented for the node processing time and the network speed.>