Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Ranjith Subramanian

dblp:10/2706 · DBLP profile ↗
← Back
3ranked-venue papers
1as first author
0since 2021 · last 2009
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 2Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 100%
Software engineering, system software, and programming languages
1 paper
Software testing · 100%
Databases, data mining, and information retrieval
1 paper
Data models and query languages · 100%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Software testing › test generation
constraint-based test generation
0.112007
Scalable automatic test data generation from modeling diagrams · ASE 2007
Software testing
test input generation
0.112007
Scalable automatic test data generation from modeling diagrams · ASE 2007
Memory systems › cache management
adaptive cache management
0.112006
Adaptive Caches: Effective Shaping of Cache Behavior to Workloads · MICRO 2006
Memory systems
cache
0.112006
Adaptive Caches: Effective Shaping of Cache Behavior to Workloads · MICRO 2006
Memory systems › cache management
cache replacement
0.112006
Adaptive Caches: Effective Shaping of Cache Behavior to Workloads · MICRO 2006
Data models and query languages
conceptual modeling
0.012007
Scalable automatic test data generation from modeling diagrams · ASE 2007
Memory systems › memory hierarchy
cache hierarchy
0.012006
Adaptive Caches: Effective Shaping of Cache Behavior to Workloads · MICRO 2006

Methods — techniques the papers use, named apart from their topics

polynomial-time consistency checking · 0.1constraint solving · 0.1SAT solving · 0.1partial tags · 0.1LRU · 0.1LFU · 0.1
YearPublicationVenuePosition
2009 Scalable satisfiability checking and test data generation from modeling diagrams
Yannis Smaragdakis, Christoph Csallner, Ranjith Subramanian
Autom. Softw. Eng.3
2007 Scalable automatic test data generation from modeling diagrams
abstract
We explore the automatic generation of test data that respect constraints expressed in the Object-Role Modeling(ORM) language. ORM is a popular conceptual modelinglanguage, primarily targeting database applications, withsignificant uses in practice. The general problem of evenchecking whether an ORM diagram is satisfiable is quitehard: restricted forms are easily NP-hard and the problemis undecidable for some expressive formulations of ORM.Brute-force mapping to input for constraint and SAT solversdoes not scale: state-of-the-art solvers fail to find data to satisfy uniqueness and mandatory constraints in realistic time even for small examples. We instead define a restricted subset of ORM that allows efficient reasoning yet contains most constraints overwhelmingly used in practice. We show that the problem of deciding whether these constraints are consistent (i.e., whether we can generate appropriate test data) is solvable in polynomial time, and we produce a highly efficient (interactive speed) checker. Additionally, we analyze over 160 ORM diagrams that capture data models from industrial practice and demonstrate that our subset of ORM is expressive enough to handle their vast majority
Yannis Smaragdakis, Christoph Csallner, Ranjith Subramanian
ASE3
2006 Adaptive Caches: Effective Shaping of Cache Behavior to Workloads
abstract
We present and evaluate the idea of adaptive processor cache management. Specifically, we describe a novel and general scheme by which we can combine any two cache management algorithms (e.g., LRU, LFU, FIFO, Random) and adaptively switch between them, closely tracking the locality characteristics of a given program. The scheme is inspired by recent work in virtual memory management at the operating system level, which has shown that it is possible to adapt over two replacement policies to provide an aggregate policy that always performs within a constant factor of the better component policy. A hardware implementation of adaptivity requires very simple logic but duplicate tag structures. To reduce the overhead, we use partial tags, which achieve good performance with a small hardware cost. In particular, adapting between LRU and LFU replacement policies on an 8-way 512KB L2 cache yields a 12.7% improvement in average CPI on applications that exhibit a non-negligible L2 miss ratio. Our approach increases total cache storage by 4.0%, but it still provides slightly better performance than a conventional 10-way set-associative 640KB cache which requires 25% more storage
Ranjith Subramanian, Yannis Smaragdakis, Gabriel H. Loh
MICRO1