Demo Data from VLDB 2026 / reviewers in the wild / expert
Shin-Ichiro Yamada
dblp:10/3667
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1988
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 68% Memory systems · 16% Storage systems · 16% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture › special-purpose processor
prolog machine architecture |
0.0 | 1 | 1988 | High-Speed CAM-Based Architecture for a Prolog Machine (ASCA) · IEEE Trans. Computers 1988 |
Memory systems
content-addressable memory |
0.0 | 1 | 1988 | High-Speed CAM-Based Architecture for a Prolog Machine (ASCA) · IEEE Trans. Computers 1988 |
Storage systems › flash and SSD › flash memory management
garbage collection |
0.0 | 1 | 1988 | High-Speed CAM-Based Architecture for a Prolog Machine (ASCA) · IEEE Trans. Computers 1988 |
Processor architecture and microarchitecture › pipelining
pipelined execution |
0.0 | 1 | 1988 | High-Speed CAM-Based Architecture for a Prolog Machine (ASCA) · IEEE Trans. Computers 1988 |
Methods — techniques the papers use, named apart from their topics
pipelining · 0.0content-addressable memory · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1988 | High-Speed CAM-Based Architecture for a Prolog Machine (ASCA)abstractA content addressable memory (CAM)-based machine architecture is proposed for a high-speed Prolog machine. This Prolog machine attempts to speed up the total Prolog execution performance by using a hierarchical pipelined scheme and a CAM-based backtracking scheme. The hierarchical pipelined scheme reduces the total number of Prolog execution steps to half of that using the conventional method. The CAM-based backtracking is efficiently and quickly achieved by using CAM's sophisticated garbage collection function, which eliminates the need for stacks and additional operation cycles. In this machine, all Prolog execution can be simply controlled by a semantic information 'inference depth' without any address handling by storing all working information, binding and control information, in CAMs. This machine attains a performance of 100 KLIPS (kilo logical inference per second) on the deterministic append program in the interpretive mode, and also attains high performance in the nondeterministic program.> Jiro Naganuma, Takeshi Ogura, Shin-Ichiro Yamada, Takashi Kimura |
IEEE Trans. Computers | 3 |