Demo Data from VLDB 2026 / reviewers in the wild / expert
R. Mike Lea
dblp:10/4904
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 1996
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Applied, interdisciplinary, general and emerging computing · 2 · 1 first-authorSystems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Parallel and multicore computing · 78% Processor architecture and microarchitecture · 22% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing › parallel architecture
massively parallel processing |
0.0 | 1 | 1996 | A modular massively parallel computing approach to image-related processing · Proc. IEEE 1996 |
Parallel and multicore computing
parallel programming models |
0.0 | 1 | 1996 | A modular massively parallel computing approach to image-related processing · Proc. IEEE 1996 |
Processor architecture and microarchitecture
SIMD |
0.0 | 1 | 1996 | A modular massively parallel computing approach to image-related processing · Proc. IEEE 1996 |
Parallel and multicore computing › parallel architecture
associative processor |
0.0 | 1 | 1991 | Associative massively parallel computers · Proc. IEEE 1991 |
Parallel and multicore computing › parallel architecture
massively parallel processor |
0.0 | 1 | 1991 | Associative massively parallel computers · Proc. IEEE 1991 |
Parallel and multicore computing
parallel architecture |
0.0 | 1 | 1991 | Associative massively parallel computers · Proc. IEEE 1991 |
Methods — techniques the papers use, named apart from their topics
wafer-scale integration · 0.0VLSI · 0.0SIMD · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1996 | A modular massively parallel computing approach to image-related processingabstractA modular massively parallel computing (Modular-MPC) philosophy to image-related processing is discussed in this paper The approach is based on application-specific configurations of generic fine-grain Single Instruction stream operating on Multiple Data (SIMD) streams massively parallel computing modules to achieve high performance and maximal flexibility and programmability while remaining cost-effective. The need for a software architecture to allow programming such systems is highlighted and the implementations on current Modular-MPC systems are described. The experience with ASTRA, a Modular-MPC testbed system, in image related application development and system performance has led to a technology road-map using VLSI, MCM, and monolithic WSI technologies aiming at 'future proofing' of the Modular-MPC concept and systems achieving T (10/sup 12/) operations per second performance. This experience and progress are discussed together with the implementation of three image-related processing applications. Anargyros Krikelis, R. Mike Lea |
Proc. IEEE | 2 |
| 1991 | Associative massively parallel computersabstractAssociative processing architectures as candidates for second-generation massive parallel computers (MPCs) are discussed. The authors outline the principle of operation of associative processors, and briefly review their development. They explore the associative string processor (ASP) architecture as a representative case study in the development of a second-generation MPC.> R. Mike Lea, Ian P. Jalowiecki |
Proc. IEEE | 1 |
| 1988 | An associative string processor architecture for parallel processing applications
Anargyros Krikelis, R. Mike Lea |
Microprocess. Microprogramming | 2 |