Demo Data from VLDB 2026 / reviewers in the wild / expert
Vishal J. Mehta
dblp:10/4941
· DBLP profile ↗
3ranked-venue papers
3as first author
0since 2021 · last 2009
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test › fault diagnosis › logic diagnosis
delay fault diagnosis |
0.2 | 2 | 2009 | Timing-Aware Multiple-Delay-Fault Diagnosis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2009 Improving the Resolution of Single-Delay-Fault Diagnosis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008 |
Electronic design automation
hardware verification and test |
0.2 | 2 | 2009 | Timing-Aware Multiple-Delay-Fault Diagnosis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2009 Improving the Resolution of Single-Delay-Fault Diagnosis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008 |
Electronic design automation › hardware verification and test
test generation |
0.1 | 2 | 2009 | Timing-Aware Multiple-Delay-Fault Diagnosis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2009 Improving the Resolution of Single-Delay-Fault Diagnosis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008 |
Methods — techniques the papers use, named apart from their topics
timing-aware ATPG · 0.2n-detection ATPG · 0.2failure log analysis · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2009 | Timing-Aware Multiple-Delay-Fault DiagnosisabstractWith feature sizes steadily shrinking, manufacturing defects and parameter variations often cause design timing failures. It is essential that those errors be correctly and quickly diagnosed. In this paper, we analyze the multiple-delay-fault diagnosis problem and propose a novel approach to solve it. We enhance the diagnostic resolution by processing failure logs at various slower-than-nominal clock frequencies. We evaluate the utility ofn-detection and timing-aware automatic-test-pattern-generated (ATPG) sets. Experimental results show that using timing-aware ATPG sets yields better diagnostic resolution and results in better delay-defect-size estimations compared ton-detection ATPG sets. We experimentally determined our diagnosis algorithm's sensitivity to delay variations. Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2008 | Improving the Resolution of Single-Delay-Fault DiagnosisabstractWith feature sizes steadily shrinking, manufacturing defects and parameter variations often cause design-timing failures. It is essential that those errors be correctly and quickly diagnosed. The existing delay-fault diagnosis algorithms cannot identify delay faults that require nonrobust test patterns due to incorrect emulation of the failure analyzer's behavior. We propose a novel approach to performing delay-fault diagnosis for robust and nonrobust tests. We enhance the diagnostic resolution by utilizing passing patterns, processing failure logs at various slower frequencies, and applying n-detection and timing-aware automatic test pattern generation sets. Experimental results show that our approach can diagnose delay faults with good resolution. The algorithm is stable with respect to delay variations that manufactured chips might experience. Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2006 | Timing Defect Diagnosis in Presence of Crosstalk for Nanometer TechnologyabstractWith feature sizes shrinking, manufacturing defects and parameter variations often cause design timing failures. Crosstalk coupling is one of such causes. It is essential that timing failures be correctly and quickly diagnosed. The authors present a methodology to diagnose the delay-defect in presence of crosstalk, given the physical information such as crosstalk coupling capacitance, neighborhood information and SDF delay information. The authors provide diagnosis results for 180, 130, 90 and 65 nm technologies Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski |
ITC | 1 |