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This 130nm Itanium® 2 processor implements the Explicitly Parallel Instruction Computing (EPIC) architecture and features an on-die 6MB, 24-way set associative L3 cache. The 374mm2 die contains 410M transistors and is implemented in a dual-Vt process with 6 layers copper interconnect and FSG dielectric. The processor runs at 1.5GHz at 1.3V and dissipates a maximum of 130W. This paper reviews circuit design and package details, power delivery, RAS, DFT and DFM features, as well as an overview of the design and verification methodology. The fuse-based clock de-skew circuit achieves 24ps skew across the entire die, while the scan-based skew control further reduces it to 7ps. The 128-bit front-side bus supports up to 4 processors on a single bus with a bandwidth of up to 6.4GB/s.

The Itanium processor is Intel's first 64-bit microprocessor [1] and features a highly parallel architecture fabricated using the 0.18um process.This higher integration of features requires a significant silicon real estate and high clock loading.These factors, coupled with more prominent on-die variations because of reduced device geometries, call for special techniques to manage the clock design.The Itanium processor employs very well balanced clock routing along with distributed deskew buffers (DSK) to achieve low skew.The Itanium™ processor also includes additional features to aid performance tuning and timing debug.This paper highlights the salient features of the Itanium processor clock design and presents clock characterization data from initial silicon.