Non-idealities of the track-and-hold (T&H) circuit in analog-to-digital converters (ADCs) can severely limit the ADC linearity. In practical applications, traditional calibration techniques are ineffective in suppressing these effects due to the multi-dimensional dependency of the non-idealities on e.g., input voltage, frequency and temperature. To address this, we propose a calibration solution that combines circuit knowledge of the error mechanisms with a data-driven approach into a shallow neural network (NN) containing just 5 neurons. Due to the small size of the NN, the output of the network can be interpreted and referred back to the underlying circuit non-idealities improving the predictability and reliability of the model. The effectiveness of the NN-based calibration is verified on silicon measurements of 10 different 12-bit SAR ADC samples manufactured in a 65nm CMOS technology, demonstrating an average improvement up to 6.8dB and 13.3dB on the measured SNDR and SFDR, respectively. To the best of the author’s knowledge, this is the first demonstration of a compact, interpretable NN-based calibration solution tested over amplitude, frequency, and temperature for multiple samples, while maintaining physics-based insight into the correction process.

This work introduces SENSOTERIC, a multi-partner project that aims at leveraging the properties of emerging Reconfigurable Field Effect Transistors (RFETs) to develop a sensor platform. RFETs will be used for a generic sensor interface and for a dedicated transducer element. In the first case, our goal is to develop an analog front-end interface that can be tuned at runtime to adapt to different environmental conditions and be used in a broad spectrum of applications. This feature shall be enabled by the polarity-control and negative differential resistance characteristics of the reconfigurable devices employed, that are co-integrable on industrial CMOS processes such as 22 nm FDSOI. In the second case, we want to exploit the intrinsic nature of these doping-free devices to yield better 1/f noise performances when compared to classic CMOS transducers. Moreover, the presence of un-gated areas on top of the channel of these devices makes them the perfect candidates to be functionalized. In this early-stage overview of the project, we will introduce the key features and the vision that make SENSOTERIC a unique contribution towards smart sensing solutions in environmental monitoring and healthcare.

In this work, a test chip for a 32 channel ultrasound imaging digitizer for intra-cardiac echocardiography is presented. The focus of this design is on area- and power efficiency, as well as multi-purpose usage for various catheters. It contains 32 individual analog front-ends and 12 bit SAR ADCs operating at 40MS/s to enable off-chip digital beamforming. The analog front-end is programmable in power, bandwidth, gain and can be partially bypassed. The front-end bypass and slew-rate can be dynamically adjusted to save power during a receive period. On-chip supply regulation is included, which can be duty-cycled between receive periods to power down the system and save power. This leads to a power supply consumption between 4.5 and 14.1mW when always on, or between 0.37 and 1.15mW when duty-cycling at an 8% ratio. When operating at maximum power, an SFDR of 57.5dB and SNR of 56.1dB are achieved.The ADC performance can optionally be improved by clocking the array in 4 separate clock phases, resulting in lower peak currents, less power supply disturbance and an overall linearity improvement of 6dB. The 32 channel array occupies 1mm2 including decoupling capacitance, combining low area and low power operation.

This paper proposes an input range boosting technique for successive-approximation-register (SAR) analog-to-digital converters (ADC). By performing a pre-comparison and switching the DAC accordingly, the input range of a SAR ADC can be doubled with limited power and area overhead. This effectively improves the power efficiency by relaxing the noise requirement and improves the area efficiency by using less DAC capacitors. A prototype ADC is fabricated in 65 nm CMOS and occupies an area of 0.0033 mm2. It consumes$34.06\ \mu\mathrm{W}$at 10 MHz sampling rate from a 1 V supply. The measured SNDR is 62 dB for a 5 MHz bandwidth, resulting in a Walden figure of merit ($\text{FoM}_{W}$) of 3.28 fJ/conversion step.

This paper proposes a passive switched-capacitor single-ended-to-differential-converter (SDC) as a front-end of a differential SAR ADC, such that it can convert single-ended input signals. As the SDC is passive, the overall solution is power-efficient compared to active SDC solutions, and is especially suitable for lower/medium resolutions. As opposed to active SDC solutions with a static bias current, the proposed switched-capacitor network only consumes dynamic power, such that its consumption scales linearly with the sampling frequency. This paper discusses the basic concept of the proposed scheme, and analyzes the impact of noise and other imperfections, describes the trade-offs for power and area, and discusses the consequences for the input driver. A prototype implementation in 65nm CMOS achieves a figure-of-merit of 6.1fJ/conversion-step at 20MS/s, while reaching an SNDR of 54.7dB up to Nyquist and occupying a chip area of only$60~\mu \text{m}\,\,\times 36~\mu \text{m}$.

This work presents a reconfigurable delay and redundancy technique, which relaxes the reference driver requirements for a charge-redistribution SAR ADC. By selectively adding delay to the most critical SAR cycle, the overall speed of the ADC is only slightly degraded, while the output impedance of the driver or the amount of decoupling capacitance can be reduced substantially. In a simulated 10-bit 10 MS/s SAR ADC prototype, the proposed technique reduces the decoupling capacitance by 16× while maintaining 59.2 dB SNDR and 71.2 dB SFDR at a power consumption of $32 \mu \mathrm{W}$. The estimated area is 0.002 mm2including decoupling capacitors.

An ultra-low power, energy efficient, and versatile resistive sensor interface for energy constrained internet-of-things applications is presented. The sensor interface includes an efficiently duty-cycled current digital-to-analog converter (I-DAC) and an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC), which enables a fully-dynamic operation. A fast start-up circuit is used in the duty-cycled I-DAC to speed up the start-up procedure and to minimize the energy consumption. A system-level correlated double sampling (CDS) technique is employed to suppress ADC offset and 1/$f$noise. To tackle the limited robustness against supply and temperature variations observed in a previous implementation of the sensor interface, a system-level ratiometric measurement (SRM) approach is employed in an updated design, which is described here in detail. The chip is fabricated in 65nm CMOS technology. Thanks to the all-dynamic nature, measurement rates from 0.1S/s to 12.5kS/s can be supported with an inherent scaling of power over 3 orders of magnitude. A reported lowest power consumption of 0.32nW is achieved at 0.1S/s. Adaptable resolution with efficient scaling of power can also be achieved by adjusting sensor interface settings and/or using oversampling and averaging. The achieved figure-of-merit (FoM), which ranges from 98 to 552fJ/conv-step is also the lowest among prior designs. Thanks to the SRM approach, only 3.6%/V and 21ppm/$^\circ \text{C}$supply and temperature sensitivity are obtained, respectively.

This paper presents an ultrasound rangefinder system able to find relative distances among energy-constrained sensor nodes. The nodes build a swarm that is operated in collision and multipath rich environments. A new distance measurement technique combining Wake-up and Frequency Modulated Continuous Wave (FMCW) is proposed to enable the ranging while neglecting the echoes from passive reflectors in the environment. The building blocks of the sensor nodes comprise a transmitter, a wake-up receiver, and a ranging receiver, all implemented in a 65 nm CMOS technology. The transmitter includes two switched-capacitor converters and an output multiplexer to generate a four-level driving signal and broadcast either a wake-up sequence or a digitally synthesized ultrasound Chirp. The transmitter dissipates 0.43 μJ and 0.82 μJ to broadcast the wake-up signal and the Chirp, respectively. A mixer first architecture is exploited in the wake-up receiver to reduce the always-on power consumption of the nodes. The ranging receiver uses a heterodyne architecture suited for the FMCW. The power consumption of the wake-up receiver and ranging receiver is 23.6 nW and 0.56 μW, respectively. The proposed rangefinder is experimentally characterized up to a 1 m distance in air and dissipates 1.25 μJ per measurement, achieving a resolution of 18.7 mm at 0.55 m.

A circuit-design-driven tool with a hybrid design automation approach for asynchronous SAR ADCs in IoT applications is presented. To minimize the circuit design time while still being able to maintain ADC performance, the hybrid approach allocates automation and manual effort properly for each block: fully-synthesized control logic, highly-automated DAC and S&H circuit, library-based comparator and template-based layout generation. A user interface governs the automated design flow from specification and circuit implementation to layout generation. Two prototypes are generated using the proposed flow in 40nm CMOS: an 8b 32MS/s and a 12b 1MS/s SAR ADC. The measured and the simulated ADC performance are in good agreement, showing the robustness of the proposed method. At 1V supply, two chips consume 187μW and 16.7μW, achieving 30.7fJ/conversion.step and 18.1fJ/conversion.step respectively.

In this paper, a hybrid design automation tool for asynchronous successive approximation register analog-to-digital converters (SAR ADCs) in Internet-of-Things applications is presented. The circuit design-driven tool uses a topdown design approach and generates circuits from specification to layout automatically. A hybrid approach is introduced for different circuits of a SAR ADC: fully synthesized control logic; a script-based flow combining equations, library, and templatebased design for the digital-to-analog converter; a lookup table approach combined with selective simulation-based fine tuning and template-based layout generation for the sample and hold; library-based comparator design and script-based layout generation. By balancing the automation and manual effort, the circuit design time is reduced from days down to minutes while still being able to maintain ADC performance. The proposed flow generated two ADC prototypes in 40-nm CMOS, an 8-bit 32 MS/s and a 12-bit 1 MS/s SAR ADC, and enabled excellent power efficiency. The two ADCs consume 187 and 16.7 μW at 1-V supply voltage, achieving 30.7 and 18.1 fJ/conversion-step, respectively.

The Phoenix1project aims to develop a new approach to explore unknown environments, based on multiple measurement campaigns carried out by extremely tiny devices, called agents, that gather data through multiple sensors. These low power and low resource agents are configured specifically for each measurement campaign to achieve the exploration goal in the smallest number of iterations. Thus, the main design challenge is to build agents as much reconfigurable as possible. This paper introduces the Phoenix project in more details, and presents first developments in the agent design.

This paper presents a 0.9V-VDD sub-nW CMOS voltage reference based on dynamic operation with the absence of large resistors, hence occupying small chip area. The proposed voltage reference is based on the threshold voltage difference between high-Vt and normal-Vt transistors. Switched capacitors are used instead of resistors to reduce chip area and to enable dynamic operation. Moreover, the dynamic operation can achieve a low average power while still supporting a large active power, needed to overcome leakage side-effects during the active period. A current biasing scheme is introduced to guarantee a proper operating point and to stabilize performance as well as power consumption over a large temperature range from -40 to 125°C. The simulated voltage reference in 65nm CMOS consumes 0.33nW at room temperature and maintains sub-nW throughout the temperature range with 2.34% active time. At 5 corners, the reference voltage Huctuates with 3% at room temperature and the temperature coefficient varies from 5.3~31.3ppm/°C. The resistor-less voltage reference only occupies a chip area of 4600μm2. The sub-nW power consumption, small chip area and low temperature coefficient in wide temperature range make this design an eligible voltage reference solution to low-power systems like IoT.

In this paper, a digital-to-time converter (DTC) assisting a time-to-digital converter (TDC) as a fractional phase error detector in an ultra-low power ADPLL is proposed and demonstrated in 40nm CMOS. A phase prediction algorithm via the assistance of the DTC reduces the required TDC range, thus saving substantial power. Additionally, a fully digital calibration algorithm is presented and proved to validate the whole ADPLL system and improve the DTC linearity. At 1 V supply voltage, the measured time resolution of the DTC is 22 ps. The TDC resolution is also indirectly measured with a closed-loop 2.4 GHz ADPLL, where -95.3 dBc/Hz in-band phase noise corresponds to a worst-case TDC resolution of 22 ps.

Good energy efficiency and area efficiency are both achieved for the presented 9-bit 35MS/s SAR ADC, by using customized small-value capacitors in a splitting monotonic switching scheme, a simplified dynamic digital logic and a self-clocked dynamic comparator. With built-in configurable gain, the ADC maintains its peak SNDR over a wide input range, featuring more flexibility. Fabricated in a 65nm CMOS technology, the ADC consumes 46.1μW at 35MS/s from 1V supply voltage, and achieves an SNDR of 51dB and an ENOB of 8.18bits at Nyquist rate, resulting in a figure of merit (FoM) of 4.5fJ/conversion-step. The core circuit only occupies 0.009mm2, which is very compact.

In this paper the architecture and performance of a co-integrated 60 GHz on-chip wireless energy harvester and ultra-low power (ULP) radio in 65-nm CMOS are discussed. Integration of an on-chip antenna with wireless power receiver and wireless data transfer module is the crucial next step to achieve compact and high efficiency fully-integrated monolithic wireless sensor nodes. A single-pole-single-throw 60 GHz RF switch is proposed and simulated to decouple the power harvesting and data transfer module. The designed on-chip RF switch has -2 dB insertion loss in EM simulations, and achieves -18 dB isolation between the energy harvesting module and the data transfer module. A single on-chip monopole antenna for power reception and data transfer is proposed with an adapted layout to reduce power coupling to undesired substrate modes. The simulated antenna shows a gain of -1.68 dBi. The power harvesting performance of the co-integrated antenna, switch and Dickson type multistage rectifier is simulated and leads to a DC output voltage of 1.2 V for -5 dBm input power at 60 GHz. With 15 dBm power transmitted to the tag at 30 GHz, the output voltage is 1.14V in the measurement. This paper is the first to demonstrate the 30 GHz mm-wave wireless energy harvesting with fully on-chip wireless energy receiver.

This paper describes the design and implementation of a low power IF frequency synthesizer which can be used in 2-tone envelope detection radios [1]. The synthesizer is based on an All-Digital PLL (AD-PLL) architecture. By means of a system noise analysis, overall noise performance is optimized while maintaining low-power operation. A current controlled ring-oscillator is designed, optimized for low-power and low phase-noise. An integer and fractional phase quantiser (PQ) is designed, where the fractional PQ is co-integrated with the oscillator to save power. The DAC, which digitally controls the oscillator, is implemented by a `coarse' and `fine' DAC topology to reduce the resolution requirement. The `fine' DAC resolution is increased by a third-order Delta-Sigma Modulator (DSM) to alleviate matching problems while maintaining monotonicity and keeping the power consumption low. Current division of the `fine' DAC, using a highly-linear current-mirror, enables fine frequency tuning while keeping low bias currents. The chip, consisting of a current controlled oscillator, `coarse' and `fine' DAC and fractional part of the phase quantiser is implemented in a 90 nm CMOS technology. The AD-PLL operates from 10 to 20 MHz and the power consumption (excluding digital loop filter and DSM) is only 19 μW at 20 MHz operation.

This paper proposes a multiple-channel frontend system with current reuse for fetal monitoring applications. The structure and specifications of the proposed frontend system are determined while taking into consideration the algorithms used for fetal electrocardiogram (fECG) detection. Two amplifier topologies based on a middle rail current source/sink (MCS) are proposed for fECG and electrohysterogram (EHG) recording. The proposed amplifiers explore power optimization in both current and voltage domain and thus achieve a better effective noise efficiency factor (NEF) while providing multiple-channels. The frontend system is designed in a 0.18μm CMOS process. Simulation results show that the frontend system provides 3 fECG and 4 EHG recoding channels with a total power consumption of 3.1μW. The IA for fECG monitoring achieves an equivalent NEF of 1.17/1.21 for low noise and low power settings respectively.

A fully differential envelope detector (ED) operating at 2.4GHz is designed in 90nm CMOS technology. The new design uses the common-gate topology to deal with large common-mode input signals through first-order current cancellation. Thereby, a fully differential ultra-low power super-regenerative front-end is enabled. It has a measured output voltage swing of 2.8–127mV and achieves 19.6dB output SNR at sensitivity input level. The circuit consumes 3µW from a 1.2V power supply.

This paper investigates the word length requirement of an analog-to-digital (ADC) converter for coherent and non-coherent detection of On-Off Keying (OOK) schemes. The paper presents closed-form expressions for coherent and non-coherent detection in terms of bit error rate in the presence of quantization noise (QN) and additive white Gaussian noise (AWGN) channels. The analytical models show that for coherent as well as non-coherent demodulation of OOK schemes in AWGN channels and affected by QN, a 4-bit ADC is able to provide close to optimum performance. As OOK is popularly being employed in event-driven radios, we extend our analysis to these radios. Our analysis shows that for event-driven radios (also referred to as wakeup radios) a 4-bit ADC is able to provide close to optimum performance. Furthermore, in the paper all the analytical models are in close agreement with the simulation results.

This paper presents a highly efficient sensitivity-based method for capacitance extraction, which models both systematic and random geometric variations. This method is applicable for BEM-based Layout Parasitic Extraction (LPE) tools. It is shown that, with only one system solve, the nominal parasitic capacitances as well as its relative standard deviations caused by both systematic and random geometric variations can be obtained. The additional calculation for both variations can be done at a very modest computational time, which is negligible compared to that of the standard capacitance extraction without considering any variation. Specifically, using the proposed method, experiments and a case study have been analyzed to show the impact of the random variation on the capacitance for a real design.

This paper presents a method for the on-chip measurement and correction of gain errors, offsets and nonlinearities of a track-and-hold circuit (T&H) of an ADC. Open-loop T&H circuits were considered in this paper because of their high-speed and low-power capabilities. However, these open-loop circuits require calibration for the aforementioned errors in order to achieve a high accuracy, especially in case of time-interleaved architectures. With the proposed method, the errors can be measured and digitized on-chip accurately, without requiring a substantial amount of hardware or any accurate references. Then, this information is used by a digitally implemented algorithm to optimize several digitally controlled analog parameters of the circuit. In turn, these parameters minimize the effect of mismatch errors. After optimization, the digital logic can be switched off completely in order to save power.

This paper presents a DAC architecture built on parallel current-steering sub-DAC entities. Two main novelties are explored: flexibility and smartness. Firstly, a number of available operating modes (op-modes) can set the overall DAC performance and functionality. These op-modes transfer some of the important design trade-offs to the end-user and constitute the DAC flexibility. The main examples include: resolution-power-number of DACs, static-dynamic performance, etc. Secondly, specific signal processing techniques become possible. The main examples of such techniques include: full self-calibration, cancellation of harmonic distortion (HD) components, and linearity improvement through redundancy. This paper concentrates on a method to suppress undesired HD components through DA processing of phase shifted replicas of the main input signal. The presented theoretical concepts are realized in a 14-bit DAC built from 4 parallel 12-bit sub-DACs. Transistor simulations and a layout design are also presented. The demonstrated flexibility characteristics of the new DAC architecture make the discussed concepts particularly suitable for FPGA integration.

This paper presents the design procedure and performance of the basic building block of a Flexible/Modular pipelined ADC. We report the advantages of adopting a flexible ADC approach [1] and we comment on the performance range that can be covered by this. Targeting a sampling frequency range from 50MS/s to 500MS/s and an accuracy range from 8b to 12b, we present and justify our design decisions leading to the implementation of the adjustable basic building block. The principle idea is the use of circuitries that can fully benefit from the speed-power consumption trade-off, while maintaining the desired accuracy. We employ dynamic circuitry and furthermore propose a fully adjustable open-loop amplifier suitable for flexible ADC realizations. Finally, we present the accuracy results and power consumption estimations along with the size of the building block implemented in a CMOS 0.18μm technology.

This paper presents the design of a digitally post-corrected open-loop front-end track-and-hold circuit for a pipelined ADC. An open-loop architecture has been selected to achieve high-speed and low power-consumption. Clock-boosting, resistive source-degeneration and cross-coupling are used to reduce low-order harmonic distortion. To further reduce distortion components in the open-loop circuit, a new digital post-correction algorithm is proposed together with a built-in self-measurement technique