Achieving race-free state assignments is an important objective in the synthesis of asynchronous sequential logic circuits (ASLCs). Traditionally, adjacency diagrams are used to help identify and resolve race conditions; however, this approach has a high degree of computational complexity. This paper presents an efficient state assignment algorithm that utilizes a pattern matching technique to predict races and to eliminate the need for enumerative searches. More specifically, the race-free state assignment problem is formulated as the embedding of a bipartite connected graph onto an n-cube and achieves a near minimum number of state variables. This algorithm has been evaluated using several representative examples. Results show that the developed algorithm provides better performance than existing algorithms. Due to the simplicity of the bipartite representation of an n-cube, the developed algorithm is suitable for ASLC synthesis that may involve a relatively large number of states.>

Asynchronous sequential logic circuits (ASLCs) are synthesized with either the Huffman model, referred to as HMASLCs, or with the signal transition graph (STG), referred to as STGASLCs. Based on a single stuck-at fault model, this paper describes fault effects for both HMASLCs and STGASLCs and addresses the similarities and differences between them. The fault effects include redundant faults and state oscillations. Input/output redundancy is a special feature of STGASLCs which relaxes the fundamental mode in HMASLCs. Results of this study show that the faults due to the input/output concurrency cannot be tested without a scan structure. This paper presents a scan design technique. ASLCScan. With this structure, the test generation problem is reduced to one of just testing the combinational logic.>

A state assignment technique is introduced for synthesizing large-scale asynchronous sequential logic circuits (ASLCs). It provides a systematic and efficient approach for generating race-free state assignments. A race condition is classified as being either an intrinsic race (IR) or or a generated race. Intrinsic races decompose into two subclassifications: visible intrinsic races and hidden intrinsic races. Algorithms have been developed to identify and eliminate these races. A graph, referred to as a Node-Weight Diagram, facilitates the process of making state assignments and guarantees that no races are generated. Moreover, it provides a convenient and efficient method for investigating the implications of selecting from an allowed set of alternative race-free state assignments. The state assignment technique described adds cycles and states, as needed, to avoid IRs and always attempts to use the minimum or near-minimum number of state variables and states. This technique has been implemented and incorporated into an ASLC design automation system. Experimental results show that it provides significantly better results than other approaches in terms of the computation time required to make the assignments and the number of state variables required to achieve race-free ASLCs.>

An attempt is made to gain a better understanding of the nature of ASIC (application-specific integrated circuit) design. This is done from a decision-making perspective, in terms of three knowledge frames: the design process, the design hyperspace, and the design repertoire. The design process frame emphasizes the hierarchical design approach and presents the methodology as a formalization of the design process. The design hyperspace concept relates to the recognition of design alternatives. Analysis techniques for evaluating algorithmic and architectural alternatives are collected and classified to form the design repertoire. This conceptual framework is an effective instrument for bridging the widening gap between system designers and VLSI technology. It also provides a conceptual platform for the development of tools for high-level architectural designs.>

A Modified CORDIC Algorithm (MCA) has been developed for the evaluation of elementary arithmetic functions. MCA incorporates increased parallelism over the original CORDIC algorithm, thus, resulting in an enhanced speed of computation. This has been accomplished by decoupling the CORDIC interation equations and transforming the sequential nature of these equations, n-bit fixed point data operands are assumed and the parameter k relates to the level of parallelism in the algorithm. The modified algorithm employs a [k+1]n2n-bit ROM for lookup tables that enable elementary arithmetic functions to be evluated in no more than [3n+2] and no less than 2 time steps. The two bounds correspond to a pipelined and a parallel implementation, respectively. The formulation of the MCA can be manipulated to obtain implementations with various speed/cost characteristics. This compares to n(3n+1)/2 time steps for the original CORDIC algorithm. For example, 32-bit ALU has k=12 and n=32; so, a 13,312-bit ROM is required to store the lookup tables, and the computation requires 98 time steps for a pipelined implementation.

This paper examines and characterizes four elemental hardware computational design alternatives (CDA's) and presents a structured approach to computational section design which incorporates a rigorous, theoretic foundation. The DIRECT CDA incorporates a single microprocessor (μP) and memory. The AU CDA contains a μP, memory, and arithmetic unit. A μP, memory, and calculator chip comprise the CALC CDA. Finally, several μP's and memories in a Master/Slave arrangement implement the multiple-μP mμP CDA. A common set of attributes - precision, speed and cost - facilitates comparison. Using these attributes, Multiattribute Utility Theory assesses a numeric quantity, the utility, to represent each CDA's relative usefulness. Thus, design involves selecting the CDA with the greatest utility.