The dAIEDGE Network of Excellence (NoE) seeks to strengthen and support the development of a dynamic European cutting-edge Artificial intelligence (AI) ecosystem under the umbrella of the European Lighthouse for AI, and to sustain the development of advanced AI. dAIEDGE fosters the exchange of ideas, concepts, and trends on cutting-edge next generation AI, creating links between ecosystem actors to help both the European Commission (EC) and the European Union (EU) and the peripheral AI constituency identify strategies for future developments in Europe. Our main objective is to advance Europe’s innovation and technology base by developing a comprehensive policy and governance approach to AI in order for the EU to become a world leader in innovation in the data economy and its applications.

The globalization of the integrated circuit (IC) supply chain has increased the risk of IC piracy. Analog and mixed-signal (AMS) ICs are particularly vulnerable, as their design demands specialized expertise and multiple tapeouts to meet specifications, while they have limited automation support and inflexible portability across technology nodes, making them valuable intellectual assets and attractive targets for piracy. IC locking has emerged as an effective countermeasure, with several AMS IC locking paradigms proposed to date. The core idea is to embed a key mechanism within the AMS IC to control its functionality, treating the key as the designer's secret. Correct operation is achieved only when the valid key is applied, while any incorrect key renders the circuit non-functional. Existing locking solutions for purely analog blocks face the challenge of ensuring this dual objective. In this work, we propose an optimizationbased methodology that jointly synthesizes the target circuit and its key mechanism, ensuring the objective is deterministically achieved. The methodology is validated on two widely used AMS circuits: a bandgap reference and an operational amplifier.

International audience

We propose a novel anti-piracy security technique for analog and mixed-signal (AMS) circuits. The circuit is re-designed by obfuscating transistors and capacitors with key-controlled versions. We obfuscate both the device geometries and their ratings, which define the maximum allowable current, voltage, and power dissipation. The circuit is designed to function correctly only with a specific key. Loading any other incorrect key degrades performance and for the vast majority of these keys the chip is damaged because of electrical over-stress. This prevents counter-attacks that employ a chip to search for the correct key. The methodology is demonstrated on a low-dropout regulator (LDO) designed in the 22nm FDSOI technology by GlobalFoundries. By locking the LDO, the entire chip functionality breaks unless the LDO is unlocked first. The secured LDO shows no performance penalty and area overhead is justifiable and less than 25%, while it is protected against all known counter-attacks in the AMS domain.

We present a novel test generation algorithm for hardware accelerators of Spiking Neural Networks (SNNs). The algorithm is based on advanced optimization tailored for the spiking domain. It adaptively crafts input samples towards high coverage of hardware-level faults. Time-consuming fault simulation during test generation is circumvented by defining loss functions targeting the maximization of fault sensitisation and fault effect propagation to the output. Comparing the proposed algorithm to the existing ones on three benchmarks, it scales up for large SNN models, and it drastically reduces the test generation runtime from days to hours and the test duration from minutes to seconds. The resultant test input shows near perfect fault coverage and has a duration equivalent to a few dataset samples, thus, besides post-manufacturing testing, it is also suited for in-field testing.

The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing.

International audience

Integrated Circuit (IC) supply chain attacks—such as piracy and intellectual property (IP) theft—pose a critical challenge for IC and System-on-Chip (SoC) designers. This paper introduces a novel anti-piracy design technique for Bluetooth Low Energy (BLE) transceivers by adapting SyncLock, an RF transceiver-specific logic locking method originally developed for Wi-Fi, to the BLE hardware architecture. The core idea of SyncLock is to key-control the transmitted frame’s preamble, ensuring that an incorrect key prevents synchronization between transmitter and receiver. We demonstrate this approach using a Continuous Phase Modulation (CPM) transmitter configured for BLE. Experimental results confirm that the proposed technique successfully achieves key-based functionality: with the correct key, normal operation is preserved and the locking mechanism remains transparent, whereas an incorrect key prevents communication link establishment. Additionally, the results show that embedding SyncLock incurs minimal and justifiable overhead, highlighting its practicality and making it a strong candidate for protecting Bluetooth transceiver hardware IPs.

As Spiking Neural Networks (SNNs) gain traction across various applications, understanding their security vulnerabilities becomes increasingly important. In this work, we focus on the adversarial attacks, which is perhaps the most concerning threat. An adversarial attack aims at finding a subtle input perturbation to fool the network’s decision-making. We propose two novel adversarial attack algorithms for SNNs: an input-specific attack that crafts adversarial samples from specific dataset inputs and a universal attack that generates a reusable patch capable of inducing misclassification across most inputs, thus offering practical feasibility for real-time deployment. The algorithms are gradient-based operating in the spiking domain proving to be effective across different evaluation metrics, such as adversarial accuracy, stealthiness, and generation time. Experimental results on two widely used neuromorphic vision datasets, NMNIST and IBM DVS Gesture, show that our proposed attacks surpass in all metrics all existing state-of-the-art methods. Additionally, we present the first demonstration of adversarial attack generation in the sound domain using the SHD dataset.

Spiking Neural Networks (SNNs) offer a promising computing paradigm suitable for low-power artificial intelligence. Spike-Timing Dependent Plasticity (STDP) is an unsupervised, biologically-inspired learning rule for SNNs. This work studies the reliability of STDP-trained SNNs under hardware faults which is largely unexplored. We present a thorough fault injection analysis of an STDP-trained SNN designed in Brian 2 simulator for MNIST classification. The analysis introduces faults in neurons and synapses before, during, and after training. We consider both permanent and transient, as well as single and multiple faults. We identify cases where the SNN exhibits inherent fault tolerance, cases where it adapts to faults through training, and cases where fault tolerance mechanisms are required,

Integrated circuit (IC) piracy and counterfeiting are a major preoccupation threat for IC designers. A powerful defense is IC locking which consists in making the IC functionality dependent on a digital key. In this work, we propose to simultaneously lock indirectly all analog and mixed-signal blocks of an IC via locking the bandgap reference (BGR) circuits that provide their biasing or reference currents or voltages. We demonstrate an obfuscated BGR in the 22nm FDSOI technology by GlobalFoundries featuring a 24-bit single secret key. Obfuscation shows no performance penalty for the valid key and less than 10% area overhead compared to the unsecured design, while guaranteeing high functionality corruption for invalid keys. The proposed obfuscation shows strong resilience against all known counter-attacks in the analog domain.

The globalization of the Integrated Circuit (IC) supply chain has given rise to several hardware security and trust threats. Especially, IC piracy and counterfeiting are significant preoccupations for designers. This demonstration shows how to secure a wireless IC against such threats. The case study is an open-source IEEE 802.11 WiFi modem implemented on hardware using a Software Defined Radio (SDR) bladeRF board. The modem is secured with synchronization-based locking (SyncLock), a state-of-the-art locking scheme for RF transceivers. SyncLock disables the wireless communication between the modem and a WiFi-compliant receiver unless the correct secret key is loaded onto the modem.

In this paper, we propose a power-efficient attention-infused convolutional neural network (CNN) hardware accelerator for RF spectrum monitoring. The AI model achieves 73.3% average accuracy across all Signal-to-Noise Ratios (SNRs) ranging from -20dB to +30dB, and a 99% accuracy for SNRs higher than 4dB using the RadioML2018 dataset . The number of parameters of the proposed attention-infused CNN is reduced by 93% compared to the baseline CNN model. An efficient hardware implementation on FPGA achieves 61 GOPS and consumes only 1191 mW. Compared to the state of the art, it achieves the highest efficiency of 51 GOPS/W.

The Internet of Things is promising as it drives the datafication of our everyday life and thus, leverages synergies between originally considered “dead” things and enables them to proactively serve humans. IoT5.0, an Artificial Intelligence assisted Internet of Things, could even more benefit society, as the devices could even learn how to provide more value. But the ubiquitous connectivity comes at a cost. Security levels have to rise tremendously to ensure a network stays secure and safe for humans. This additional effort often is a burden for small and medium sized enterprises as the complexity and security demands of such systems rise faster than available resources. Consequently., RESILIENT TRUST focuses on end-to-end security of IoT processing chains with a focus on strong exploitation for SMEs. Moreover, RESILIENT TRUST will address and significantly mitigate the major risks to enable IoT 5.0. That way., this project will be a driver for sustainable development and the generation of convenience and wealth. A solution is proposed to ensure end-to-end security by boosting RESILIENCE and TRUST along different key supply chains of IoT device.

We investigate the impact of semiconductor manufacturing process variation on the accuracy of machine learning models implemented as analog Artificial Neural Networks (ANNs). Unlike their digital counterparts, where binary operations and weight representation ensure the robustness of a trained model across software and hardware, the continuous nature of weights and operations in analog ANNs makes the accuracy of a trained model inevitably sensitive to the exact parameters of each fabricated chip. As a result, expensive chip-in-the-loop training is necessitated to ensure high accuracy. Herein, we elucidate the nature and extent of the problem using actual measurements from multiple identically fabricated copies of an analog ANN chip and a variety of trained models. We quantify the accuracy loss when models are ported across chips, as well as the effort required for individually training each chip, and we discuss strategies for containing this effort.

We propose an on-line testing methodology for neuromorphic hardware supporting spiking neural networks. Testing aims at detecting in real-time abnormal operation due to hardware-level faults, as well as screening of outlier or corner inputs that are prone to misprediction. Testing is enabled by two on-chip classifiers that prognosticate, based on a low-dimensional set of features extracted with spike counting, whether the network will make a correct prediction. The system of classifiers is capable of evaluating the confidence of the decision, and when the confidence is judged low a replay operation helps to resolve the ambiguity. The testing methodology is demonstrated by fully embedding it in a custom FPGA-based neuromorphic hardware platform. It operates in the background being totally non-intrusive to the network operation, while offering a zero-latency test decision for the vast majority of inferences.

We address the problem of testing artificial intelligence (AI) hardware accelerators implementing spiking neural networks (SNNs). We define a metric to quickly rank available samples for training and testing based on their fault detection capability. The metric measures the interclass spike count difference of a sample for the fault-free design. In particular, each sample is assigned a score equal to the spike count difference between the first two top classes. The hypothesis is that samples with small scores achieve high fault coverage because they are prone to misclassification, i.e., a small perturbation in the network due to a fault will result in these samples being misclassified with high probability. We show that the proposed metric correlates with the per-sample fault coverage and that retaining a set of high-ranked samples in the order of ten achieves near-perfect fault coverage for critical faults that affect the SNN accuracy. The proposed test generation approach is demonstrated on two SNNs modeled in Python and on actual neuromorphic hardware. We discuss fault modeling and perform an analysis to reduce the fault space so as to speed up test generation time.

We present a locking-based design-for-security methodology to prevent piracy of RF transceiver integrated circuits. The solution is called SyncLock as it locks the synchronization of the transmitter with the receiver. If a key other than the secret key is applied, synchronization and, thereby, communication fail. SyncLock is implemented using a novel locking concept consisting of two spatially separated mechanisms. A hard-coded error is hidden into the design to break synchronization while error correction, i.e., unlocking, takes place in another part of the design by applying the secret key. SyncLock offers several advantages: the secret key is unique, i.e., any incorrect key causes a denial-of-service, there is no performance penalty, it can be seemingly integrated into the digital design flow, area and power overheads are negligible, and it achieves maximum provable security thwarting all known counter-attacks. SyncLock is demonstrated with hardware measurements.

We propose a Hardware Trojan (HT) attack in wireless Integrated Circuits (ICs) that aims at leaking sensitive information within a legitimate transmission. The HT is hidden inside the transmitter modulating the sensitive information into the preamble of each transmitted frame which is used for the synchronization of the transmitter with the receiver. The data leakage does not affect synchronization and is imperceptible by the inconspicuous nominal receiver as it does not incur any performance penalty in the communication. A knowledgeable rogue receiver, however, can recover the data using signal processing that is too expensive and impractical to be used during run-time in nominal receivers. The HT mechanism is designed at circuit-level and is embedded entirely into the digital section of the RF transceiver having a tiny footprint. The proposed HT attack is demonstrated with measurements on a hardware platform. We demonstrate the stealthiness of the attack, i.e., its ability to evade defenses based on testing and run-time monitoring, and the robustness of the attack, i.e., the ability of the rogue receiver to recover the leaked information even under unfavorable channel conditions.

We propose an anti-piracy security technique based on locking for analog and mixed-signal circuits designed in FD-SOI. We show that obfuscating the body-bias voltages of tunable transistors is an effective way for inducing high functionality corruption. The obfuscation is achieved by constituting a secret key from the concatenation of the input digital codes of the body-bias generators that produce the correct body-bias voltages. We also propose a slight modification of the body-bias generator that increases prohibitively the time complexity of counter-attacks aiming at finding an approximate key. The proposed locking scheme is demonstrated on a Σ$$ modulator used in highly-digitized RF receiver architectures.

We present an anti-piracy locking-based design methodology for RF transceivers, called SyncLock. SyncLock acts on the synchronization of the transmitter with the receiver. If a key other than the secret one is applied the synchronization and, thereby, the communication fails. SyncLock is implemented using a novel locking concept. A hard-coded error is hidden into the design while the unlocking, i.e., the error correction, takes place at another part of the design upon application of the secret key. SyncLock presents several advantages. It is generally applicable, incorrect keys result in denial-of-service, it incurs no performance penalty and minimum overheads, and it offers maximum security thwarting all known counter-attacks. We demonstrate SyncLock with hardware measurements.

Despite the parallelism and sparsity in neural network models, their transfer into hardware unavoidably makes them susceptible to hardware-level faults. Hardware-level faults can occur either during manufacturing, such as physical defects and process-induced variations, or in the field due to environmental factors and aging. The performance under fault scenarios needs to be assessed so as to develop cost-effective fault-tolerance schemes. In this work, we assess the resilience characteristics of a hardware accelerator for Spiking Neural Networks (SNNs) designed in VHDL and implemented on an FPGA. The fault injection experiments pinpoint the parts of the design that need to be protected against faults, as well as the parts that are inherently fault-tolerant.

We demonstrate a Hardware Trojan (HT)-based circuit-to-circuit attack mechanism in the context of Systems-on-Chip (SoCs). The HT trigger is hidden inside the attacking circuit and the HT payload travels from the attacking circuit to the victim circuit via the test infrastructure. The common test infrastructure is configured accordingly by the HT so as to propagate the HT payload. We demonstrate the capability of this HT to perform a denial-of-service attack on an industrial Analog-to-Digital Converter (ADC) connected to a IEEE 1687 test infrastructure.

Hardware Trojan (HT) insertion is a major security threat for electronic components that demand a high trust level. Several HT attack mechanisms have been demonstrated to date, and several HT prevention and detection countermeasures have been proposed to thwart HT attacks. Given the multitude of HT attack mechanisms, run-time monitors for HT detection are used as a last line of defense. In this paper, we propose a run-time monitoring methodology for HT attack mechanisms affecting the analog and mixed-signal (AMS) sections of an Integrated Circuit (IC). The methodology is based on the Symmetry-based Built-In Self-Test (SymBIST) principle that relies on distributing invariances across the IC and continuously checking for their compliance. Detection of various HT attacks are demonstrated on a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) IP at transistor-level.

The design and manufacturing steps of a chip typically involve several parties. For example, a chip may comprise several third-party intellectual property (IP) cores and the integrated circuit (IC) fabrication may be outsourced to a third-party foundry. IP cores and ICs are shared with potentially untrusted third parties and, as a result, are subject to piracy attacks. Even more, any legally purchased chip may be reverse engineered to retrieve the design down to transistor level and, thereby, it is also subject to piracy attacks. In this article, we proposeMixLock, an anti-piracy countermeasure for mixed-signal IP cores and ICs.MixLockprotection is based on inserting a lock mechanism into the design such that correct functionality is established only after applying a key which is the designer’s secret. The lock mechanism acts on the mixed-signal performances by leveraging logic locking of the digital part.MixLockpresents several key attributes. It is generally applicable, it is nonintrusive to the sensitive analog section, it incurs no performance penalty and has very low area and power overheads, it is fully automated, and it is capable of co-optimizing security in both the analog and digital domains. We demonstrateMixLockon a$\Sigma \Delta $analog-to-digital converter (ADC) using hardware measurements and an audio demonstrator.

We propose a Hardware Trojan (HT) attack for analog circuits with its key characteristic being that it cannot be prevented or detected in the analog domain. The HT attack works in the context of Systems-on-Chip (SoCs) comprising both digital and analog Intellectual Property (IP) blocks. The attacker could be either the SoC integrator or the foundry. More specifically, the HT trigger is placed inside a dense digital IP block where it can be effectively hidden, whereas the HT payload is in the form of a digital pattern transported via the test bus or generated within the test bus, reaching the Design-for-Test (DfT) or programmability interface of the victim analog IP with the test bus. The HT payload unexpectedly activates the DfT and sets the victim analog IP into some possibly partial and undocumented test mode or changes the nominal programmability. The HT payload can be designed to result in performance degradation or complete malfunction, i.e., denial of service. We demonstrate this HT attack scenario on two analog IPs, namely a low-dropout (LDO) regulator using simulation and an RF receiver using hardware measurements.

We demonstrate an attack to break all analog circuit locking techniques that act upon the biasing of the circuit. The attack is based on re-synthesizing the biasing circuits and requires only the use of an optimization algorithm. It is generally applicable to any analog circuit class. For the attacker the method requires no in-depth understanding or analysis of the circuit. The attack is demonstrated on a bias-locked Low-Dropout (LDO) regulator. As the underlying optimization algorithm we employ a Genetic Algorithm (GA).

The error-resiliency of Artificial Intelligence (AI) hardware accelerators is a major concern, especially when they are deployed in mission-critical and safety-critical applications. In this paper, we propose a neuron fault tolerance strategy for Spiking Neural Networks (SNNs). It is optimized for low area and power overhead by leveraging observations made from a large-scale fault injection experiment that pinpoints the critical fault types and locations. We describe the fault modeling approach, the fault injection framework, the results of the fault injection experiment, the fault-tolerance strategy, and the fault-tolerant SNN architecture. The idea is demonstrated on two SNNs that we designed for two SNN-oriented datasets, namely the N-MNIST and IBM's DVS128 gesture datasets.

Fault diagnosis methodologies for analog circuits lag far behind those for their digital counterparts. In this paper, we show how the generic Symmetry-based Built-In Self-Test (BIST) (or SymBIST), originally proposed for defect-oriented post-manufacturing test and on-line test, can be seamlessly reused for the purpose of diagnosis. BIST can offer better insights into the circuit and, thereby, can assist diagnosis towards resolving ambiguity groups. Using SymBIST we demonstrate high diagnosis resolution and fast diagnosis cycle for an industrial Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC).

We propose a novel Physical Unclonable Function (PUF) concept based on a single spiking neuron. The inherent variability of the neuron results in a chip-unique analog spiking pattern that is digitized to produce a chip-unique digital key. A stability booster is also employed based on self-masking to obtain a fully stable digital key. The PUF is area and power effective since a single PUF cell is used to produce an arbitrarily sized digital key. We demonstrate PUF quality metrics close to ideal values and argue that the PUF is resilient against various physical attacks.

We treat the problem of analog integrated circuit (IC) obfuscation toward intellectual property (IP) protection against reverse engineering. Obfuscation is achieved by camouflaging the effective geometry of layout components via the use of fake contacts, which originally were proposed for gate camouflaging in digital ICs. We present a library of obfuscated layout components, we give recommendations for effective camouflaging, we discuss foreseen attacks and the achieved resiliency, and we propose security metrics for assessing the hardness of reverse engineering. The proposed methodology is demonstrated on an operational amplifier and an RF ΣΔ analog-to-digital converter (ADC).

We propose a Built-In Self-Test (BIST) paradigm for analog and mixed-signal (A/M-S) Integrated Circuits (ICs), called symmetry-based BIST (SymBIST). SymBIST exploits inherent symmetries in an A/M-S IC to construct signals that are invariant by default, and subsequently checks those signals against a tolerance window. Violation of invariant properties points to the occurrence of a defect or abnormal operation. SymBIST is designed to serve as a functional safety mechanism. It is reusable ranging from post-manufacturing test, where it targets defect detection, to on-line test in the field of operation, where it targets low-latency detection of transient failures and degradation due to aging. We demonstrate SymBIST on a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). SymBIST features high defect coverage, short test time, low overhead, zero performance penalty, and has a fully digital interface making it compatible with modern digital test access mechanisms.

We propose an antipiracy security approach for programmable analog and mixed-signal (AMS) integrated circuits (ICs). The security approach relies on functionality locking by leveraging the inherent programmability and utilizing the configuration settings as secret keys or, equivalently, the programming bits as key bits. When invalid keys are applied, the circuit is untuned and, as a result, its functionality breaks, i.e., at least one of the performances violates its specification. As long as the calibration algorithm that produces the configuration settings can be kept secret, the proposed approach can serve as a countermeasure against all types of counterfeiting, i.e., cloning, overbuilding, remarking, and recycling. An important advantage of the proposed approach is that it is lock-less. It leaves the design intact, there is no change to the design flow, and there are no performance penalty and no area or power overheads due to the lock operation. We demonstrate it on a$\Sigma \Delta $analog-to-digital converter (ADC) with 194-bit programmability and complex calibration algorithm used in the context of highly digitized, multistandard RF receivers.

In this paper, we demonstrate a security approach for the class of highly-programmable analog Integrated Circuits (ICs) that can be used as a countermeasure for unauthorized chip use and piracy. The approach relies on functionality locking, i.e. a lock mechanism is introduced into the design such that unless the correct key is provided the functionality breaks. We show that for highly-programmable analog ICs the programmable fabric can naturally be used as the lock mechanism. We demonstrate the approach on a multi-standard RF receiver with configuration settings of 64-bit words.

In this paper, we propose a defect-oriented Built-In Self-Test (BIST) paradigm for analog and mixed-signal (A/MS) Integrated Circuits (ICs), called symmetry-based BIST (Sym-BIST). SymBIST exploits inherent symmetries into the design to generate invariances that should hold true only in defect-free operation. Violation of any of these invariances points to defect detection. We demonstrate SymBIST on a 65nm 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) IP by ST Microelectronics.

We present a Hardware Trojan (HT) attack scenario for analog circuits. The characteristic of this HT is that it does not reside inside the victim analog circuit. Instead, it resides on an independent digital circuit on the same die where it is triggered, yet its payload is applied only to the analog circuit after being transferred via the common test infrastructure and the test interface of the analog circuit. This HT attack cannot be detected or prevented in the analog domain and it exploits the dense digital circuit to hide effectively its footprint.

The deployment of Artificial Intelligence (AI) hardware accelerators in a variety of applications, including safety-critical ones, requires assessing their inherent reliability to hardware-level faults and developing cost-effective fault tolerance techniques. This entails performing large-scale fault simulation experiments. However, transistor-level fault simulation is prohibitive and fault simulation should be carried out at a higher abstraction level. In this work, we focus on spiking neural networks (SNNs), and we follow a bottom-up approach starting from transistor-level simulations for developing a neuron behavioral-level fault model that can be readily employed for performing behavioral-level fault simulation of deep SNNs.

In this paper, we propose a hardware security methodology for mixed-signal Integrated Circuits (ICs). The proposed methodology can be used as a countermeasure for IC piracy, including counterfeiting and reverse engineering. It relies on logic locking of the digital section of the mixed-signal IC, such that unless the correct key is provided, the mixed-signal performance will be pushed outside of the acceptable specification range. We employ a state-of-the-art logic locking technique, called Stripped Functionality Logic Locking (SFLL). We show that strong security levels are achieved in both mixed-signal and digital domains. In addition, the proposed methodology presents several appealing properties. It is non-intrusive for the analog section, it incurs reasonable area and power overhead, it can be fully automated, and it is virtually applicable to a wide range of mixed-signal ICs. We demonstrate it on a ΣΔ Analog-to-Digital Converter (ADC).

Over the last decade there has been a surge of activity in employing advanced statistical analysis and machine learning methods to various test-related tasks. The topic is no longer simply a matter of academic curiosity but, rather, a pressing need of the industry as it seeks to address various challenges. In this session, three industry experts have been invited to give their perspective, describe machine learning use cases, and discuss challenges and future work ideas. The three talks will cover the use of deep learning for hotspot detection, the challenge of rendering machine learning-based decisions in the semiconductor industry trustable and explainable, and data analytics across the the complete product cycle towards improved product reliability.

In recent years, a large number of works have surfaced demonstrating applications of machine learning in the field of integrated circuit testing. Many of these works showcase the effectiveness of machine learning compared to the current industry practice on actual case studies with industrial data. The aim of the paper is to offer a concise and comprehensive tutorial on machine learning applications in integrated circuit testing and to provide some practical recommendations for practitioners.

The paper aims at stimulating a discussion on the prospect and potentiality of open source electronic design automation tools and open source hardware. We discuss the benefits and motivation, as well as the expected difficulties and shortcomings. Finally, we provide a representative list of efforts as of today specifically for analog and mixed-signal circuits and systems design and prototyping.

This special session will discuss how machine learning can transform test. The first talk will review the key challenges and will argue whether contemporary tools, such as deep learning, could offer any advantages over traditional methods. The second talk will focus on extracting useful information from big test data. The third talk will view adaptive test as running machine learning algorithms in real time on big data.

The standard approach in industry for post-manufacturing testing of mixed-signal circuits is to measure the performances that are included in the data sheet. Despite being accurate and straightforward, this approach involves a high test time since there are numerous performances that need to be measured sequentially by switching the circuit into different test configurations. Adaptive test is a new test paradigm that still adheres to the standard approach, but it adjusts it on-the-fly to the particularities of the circuit under test so as to better control test time and to achieve robust outlier detection. In this paper, we present an adaptive test flow for mixed-signal circuits that has comprehensive user-defined parameters to span the tradeoff between test time savings and fault coverage so as to select an advantageous point on the curve based on test economics. The flow also provides robust test escape risk estimation so as to add confidence to the test process. The proposed idea is demonstrated on a sizable production dataset from a large mixed-signal circuit.

On behalf of the Program, Organizing, and Steering Committees, we would like to extend a warm welcome to everyone attending the European Test Symposium 2017 (ETS'17). ETS has been established as one of the main international forums and the larger forum in Europe that brings together the test community to discuss emerging ideas, views, and trends in the area of electronic-based circuits and system testing. Topics of interest include, but are not limited to, design-for-test, dependability, security, failure analysis and diagnosis, on-line test, automated test hardware, validation and verification, fault simulation, fault tolerance, automatic test generation, etc.

Adaptive test is a promising direction for reducing the manufacturing test cost. It aims to dynamically adjust the test program on a device-by-device or on a wafer-by-wafer basis. Adjusting the test program could involve eliminating tests, changing test limits, re-ordering tests, etc. The objective is to spend the minimum possible test time per device without sacrificing fault coverage. In this paper, we present an adaptive test flow for mixed-signal ICs and we demonstrate its effectiveness on a sizable production dataset from a large mixed-signal IC. The adaptive test flow first eliminates seemingly redundant tests on a wafer-by-wafer basis and then it may refine the test content on a device-by-device basis so as to ensure high fault coverage. In addition, it estimates the test escape risk so as to provide confidence in the binning of devices.

Yield estimation is an indispensable piece of information at the onset of high-volume production of a device, as it can inform timely process and design refinements in order to achieve high yield, rapid ramp-up, and fast time-to-market. To date, yield estimation is generally performed through simulation-based methods. However, such methods are not only very time-consuming for certain circuit classes, but also limited by the accuracy of the statistical models provided in the process design kits (PDKs). In contrast, herein we introduce yield estimation solutions which rely exclusively on silicon measurements and we apply them toward predicting yield during: 1) production migration from one fabrication facility to another and 2) transition from one design generation to the next. These solutions are applicable to any circuit, regardless of PDK accuracy and transistor-level simulation complexity, and range from rather straightforward to more sophisticated ones, capable of leveraging additional sources of silicon data. Effectiveness of the proposed yield forecasting methods is evaluated using actual high-volume production data from two 65-nm RF transceiver devices.

On behalf of the Steering, Program and Organizing Committees, we would like to welcome you to the European Test Symposium 2016 (ETS'16); the largest event in Europe entirely devoted to presenting and discussing scientific trends, emerging results, hot topics, and applications in the area of electronic circuit and system testing. ETS'16 is the 21st edition of the symposium and is held in Amsterdam, The Netherlands. Amsterdam is the capital and most populous city of the Kingdom of the Netherlands. Amsterdam's name derives from Amstelredamme, indicative of the city's origin as a dam of the river Amstel.

Yield estimation is an indispensable piece of information at the onset of high-volume manufacturing (HVM) of a device. The increasing demand for faster time-to-market and for designs with growing quality requirements and complexity, requires a quick and successful yield estimation prior to HVM. Prior to commencing HVM, a few early silicon wafers are typically produced and subjected to thorough characterization. One of the objectives of such characterization is yield estimation with better accuracy than what pre-silicon Monte Carlo simulation may offer. In this work, we propose predicting yield of a device using information from a similar previous-generation device, which is manufactured in the same technology node and in the same fabrication facility. For this purpose, we rely on the Bayesian Model Fusion (BMF) technique. The effectiveness of the proposed methodology is evaluated using sizable industrial data from two RF devices in a 65nm technology.

This paper presents an Embedded Test Instrument (ETI) for the estimation of the High Frequency (HF) jitter of an observed clock signal. The ETI uses a second reference clock for under-sampling the observed signal similar to previous approaches. However, the analysis of the test response does not require the construction of the Cumulative Distributed Function (CDF) of the jitter as in previous approaches. Instead, the HF jitter of the input observed signal is transformed at the output of the ETI into a digital value that corresponds to a number of unwanted signal transitions. We demonstrate in this paper that the transfer function of the ETI defined by the ratio of the number of unwanted signal transitions and the input HF jitter is linear. This property leads to a simple circuit implementation. The linearity of the ETI is demonstrated firstly by behavioral simulation, using a theoretical model of the output of the under-sampling process, and secondly by transistor-level simulation using the 65 nm CMOS bulk technology by ST Microelectronics. We also present experimental measurements that have been carried out using an FPGA-based test platform to validate the linearity of the transfer function in the presence of non-idealities that can affect the ETI. Finally, we demonstrate the exploitation of the ETI within Systems-on-Chip (SoCs) produced in highvolume by ST Microelectronics.

Yield estimation is an indispensable piece of information at the onset of high-volume production of a device. It can be used to refine the process/design in time so as to guarantee high production yield. In the case of migration of production of a specific device from a source fab to a target fab, yield estimation in the target fab can be accelerated by employing information from the source fab, assuming that the process parameter distributions in the two fabs are similar, but not necessarily the same. In this paper, we employ the Bayesian Model Fusion (BMF) technique for efficient yield prediction of a device in the target fab. BMF adopts prior knowledge from the source fab and combines it intelligently with information from a limited number of early silicon wafers from the target fab. Thus, BMF allows us to obtain quick and accurate yield estimates at the onset of production in the target fab. The proposed methodology is demonstrated on an industrial RF transceiver.

The high cost of mixed-signal circuit testing has sparked a lot of interest for developing alternative low-cost techniques. Although it is rather straightforward to evaluate an alternative test technique in terms of test cost reduction, proving the equivalence between an alternative and the standard test technique in terms of test metrics, before actually deploying the alternative test technique in production, is very challenging. The underlying reason is the prohibitive simulation effort that is required. Existing test metrics evaluation methodologies are efficient only for circuits that can be simulated fast at transistor-level. In this paper, we propose a test metrics evaluation methodology for circuits with long simulation times that is based on a combination of behavioral modeling and statistical blockade. The methodology is demonstrated on a built-in self-test strategy for ΣΔ analog-to-digital converters.

We propose a post-fabrication calibration technique for RF circuits that is performed during production testing with minimum extra cost. Calibration is enabled by equipping the circuit with tuning knobs and sensors. Optimal tuning knob identification is achieved in one-shot based on a single test step that involves measuring the sensor outputs once. For this purpose, we rely on variation-aware sensors which provide measurements that remain invariant under tuning knob changes. As an auxiliary benefit, the variation-aware sensors are non-intrusive and totally transparent to the circuit. The technique is demonstrated on a 65nm RF power amplifier.

In the context of mission-critical, safety-critical, and remote-controlled applications, it is required to equip systems with self-adapting capabilities. Adaptation is required in post-manufacturing to correct yield loss and achieve zero defective parts-per-million as well as during normal operation to account for different application scenarios and for varying environmental conditions. A self-adaptive system must be capable of providing the required high performances after manufacturing and throughout its normal operation regardless the application scenario wherein it is deployed and despite the varying environmental conditions. In this paper, we describe a generic post-manufacturing self-adaptation technique for RF circuits as well as concurrent self-adaptation techniques for a safety-critical medical sensor for glaucoma diagnosis and for a NFC system which is very sensitive to the environment in which it operates.

Validation of an embedded test technique in terms of its expected yield loss and test escape metrics is a key step before it can be deployed in high-volume manufacturing. However, performing this validation at the design stage usually demands extensive computational resources, which may render electrical simulations infeasible. In this paper, we propose a digital test technique for dynamic test of ΣΔ ADCs based on a digital ternary stimulus together with an advanced simulation framework for its validation. The proposed simulation strategy relies on a combination of transistor-level simulations, behavioural simulations, and statistical tools. To show the feasibility of our approach, we use the proposed validation framework to compare the ternary stimulus with a digital bitstream stimulus, as well as with a standard high-resolution analog sine-wave stimulus.

The accepted approach in industry today to ensure out-going quality in high-volume manufacturing of analog circuits is to measure datasheet specifications. The lack of a comprehensive fault model that is computationally efficient makes the elimination of any tests or the use of lower-cost alternative tests too risky or too time-consuming. Monte Carlo simulations offer a general way to model parametric variations, but inherently focus on normal instead of defective performance. This paper defines a new, general fault model comprising a set of marginally failing circuit instances to evaluate parametric fault coverage of test suites in a way that reduces the number of Monte Carlo simulations by one or more orders of magnitude. As an illustrative example, the technique is applied to six parameters of an RF low-noise amplifier (LNA).

The accepted approach in industry today to ensure out-going quality in high-volume manufacturing of analog circuits is to directly measure datasheet specifications. To reduce the involved costs it is required to eliminate specification tests or use instead lower-cost alternative tests. However, this is too risky if the resultant fault coverage and yield coverage metrics of the new test approach are not estimated accurately. This paper proposes a methodology to efficiently derive a set of most probable failing and marginally functional circuit instances. Based on this set, we can readily define and estimate fault coverage and yield coverage metrics. Our methodology reduces the required number of Monte Carlo simulations by one or more orders of magnitude. As an illustrative example, the methodology is applied to a radio frequency low-noise amplifier.

The high cost of testing certain analog, mixed-signal, and RF circuits has driven in the recent years the development of alternative low-cost tests to replace the most costly or even all standard specification tests. However, there is a lack of solutions for evaluating the parametric test error, that is, the test error for circuits with process variations, resulting from this replacement. For this reason, test engineers are often reluctant to adopt alternative tests since it is not guaranteed that test cost reduction is not achieved at the expense of sacrificing test quality. In this paper, we present a technique to estimate the parametric test error fast and reliably with parts per million accuracy. The technique is based on extreme value theory and statistical blockade. Relying on a small number of targeted simulations, it is capable of providing accurate estimates of parametric test error in the general scenario where a set of alternative tests replaces all or a subset of standard specification tests.

In this summary paper, we discuss two types of sensors that provide a built-in test solution for RF circuits. The key characteristic of the sensors is that they are non-intrusive, in the sense that they are not electrically connected to the RF circuit under test. This has the important advantage that the design of the RF circuit becomes totally independent from the design of the sensors. In other words, the RF circuit design methodology and performance trade-offs are totally transparent to the insertion of the built-in test strategy. In particular, we propose variation-aware sensors to implement an implicit functional test and a temperature sensor to implement a defect-oriented test. The proposed sensors provide DC or low-frequency measurements, thus they have the potential to reduce drastically the test cost. We discuss the principle of operation of the sensors, we provide design guidelines, and we demonstrate the concept on a set of fabricated chips. To the best of our knowledge, this is the first proof-of-concept of RF test based on non-intrusive sensors.

Fault diagnosis of Integrated Circuits (ICs) has grown into a special field of interest in the Semiconductor Industry. Fault diagnosis is very useful at the design stage for debugging purposes, at high-volume manufacturing for obtaining feedback about the underlying fault mechanisms and improving the design and layout in future IC generations, and in cases where the IC is part of a larger safety-critical system (e.g. automotive, aerospace) for identifying the root-cause of failure and for applying corrective actions that will prevent failure reoccurrence and, thereby, will expand the safety features. In this summary paper, we present a methodology for fault modeling and fault diagnosis of analog circuits based on machine learning. A defect filter is used to recognize the type of fault (parametric or catastrophic), inverse regression functions are used to locate and predict the values of parametric faults, and multi-class classifiers are used to list catastrophic faults according to their likelihood of occurrence. The methodology is demonstrated on both simulation and high-volume manufacturing data showing excellent overall diagnosis rate.

We present a built-in, defect-oriented test approach for RF circuits that is based on thermal monitoring. A defect will change the power dissipation of the circuit under test from its expected range of values which, in turn, will induce a change in the expected temperature in the substrate near the circuit. Thus, an on-chip temperature sensor that monitors the temperature near the circuit can reveal the existence of the defect. This test approach has the key advantage of being non-intrusive and transparent to the design since the temperature sensor is not electrically connected to the circuit. We discuss the basics of thermal monitoring, the design of the temperature sensor, as well as the test scheme. The technique is demonstrated on fabricated chips where a temperature sensor is employed to monitor an RF low noise amplifier.

Reduced code testing of a pipeline analog-to-digital converter (ADC) consists of inferring the complete static transfer function by measuring the width of a small subset of codes. This technique exploits the redundancy that is present in the way the ADC processes the analog input signal. The main challenge is to select the initial subset of codes such that the widths of the rest of the codes can be estimated correctly. By applying the state-of-the-art technique to a real 11-bit 2.5-bit/stage, 55nm pipeline ADC, we observed that the presence of noise affected the accuracy of the estimation of the static performances (e.g, differential nonlinearity and integral non-linearity). In this paper, we exploit another feature of the redundancy to cancel out the effect of noise. Experimental measurements demonstrate that this reduced code testing technique estimates the static performances with an accuracy equivalent to the standard histogram technique. Only 6 % of the codes need to be considered which represents a very significant test time reduction.

We present a set of sensors that enable a built-in test in RF circuits. The key characteristic of these sensors is that they are non-intrusive, that is, they are not electrically connected to the RF circuit, and, thereby, they do not degrade its performances. In particular, the presence of spot defects is detected by a temperature sensor, whereas the performances of the RF circuit in the presence of process variations are implicitly predicted by process sensors, namely dummy circuits and process control monitors. We discuss the principle of operation of these sensors, their design, as well as the test strategy that we have implemented. The idea is demonstrated on an RF low noise amplifier using post-layout simulations.

This tutorial paper describes novel scalable, nonlinear/generic, and industrially-oriented approaches to perform variation-aware modeling, verification, fault simulation, and testing of analog/custom ICs. In the first section, Dimitri De Jonghe, Elie Maricau, and Georges Gielen present a new advance in extracting highly nonlinear, variation-aware behavioral models, through the use of data mining and a re-framing of the model-order reduction problem. In the next section, Trent McConaghy describes new statistical machine learning techniques that enable new classes of industrial EDA tools, which in turn are enabling designers to perform fast and accurate PVT / statistical / high-sigma design and verification. In the third section, Bratislav Tasić presents a novel industrially-oriented approach to analog fault simulation that also has applicability to variation-aware design. In the final section, Haralampos Stratigopoulos describes describes state-of-the-art analog testing approaches that address process variability.

The reduced code linearity test technique for pipeline ADCs consists in measuring some judiciously selected codes which contain the information about the linearity of the converter as opposed to the standard histogram technique that considers indiscriminately all codes. This technique dramatically reduces the static test time for pipeline ADCs. In this paper, we identify some limitations in the existing version of the technique and we provide solutions to enhance its accuracy. The enhanced technique is applied to a 12-bit 2.5-bit/stage pipeline ADC.

This paper discusses a new type of sensors to enable a built-in test in RF circuits. The proposed sensors provide DC or low-frequency measurements, thus they can reduce drastically the testing cost. Their key characteristic is that they are nonintrusive, e.g. they are not connected electrically to the RF circuit. Thus, the performances of the RF circuit are unaffected by the monitoring operation. The sensors function as process monitors and share the same environment with the RF circuit. The underlying principle is that the sensors and the RF circuit are subject to the same process variations, thus shifts in the performances of the RF circuit can be inferred implicitly by shifts in the outputs of the sensors. We present experimental results on fabricated samples that include an LNA with embedded sensors. The samples are collected from different sites of a wafer such that they exhibit process variations. We demonstrate that the performances of the RF circuit can be predicted with sufficient accuracy through the sensors by employing the alternate test paradigm.

The trend nowadays is to integrate more and more functionalities into a single chip. This, however, has serious implications in the testing cost. Especially for the analog circuits, the testing cost tends to be very high, despite the fact they occupy a small fraction of the area of the chip. Therefore, to reduce this cost, there is a high interest to replace the most demanding tests by alternative measurements. However, such replacement may inadvertently result in accepting faulty chips or rejecting functional chips. In this paper, we present a method for estimating such test metrics in the general scenario where a single test is replaced by a single measurement. The method is based on the extreme value theory and the statistical blockade algorithm. It can be readily applied during the test development phase to obtain estimates of the test metrics and corresponding confidence intervals with parts-per-million precision. For this purpose, the method requires a small number of selective simulations that we can afford to run in practice.

In this paper we present the theory for evaluating the test error that we commit when we replace a standard analog test by a lower-cost alternative measurement. The evaluation takes place during the design and test development phases and relies on a tractable number of simulations. The test error is expressed in terms of test escape and yield loss which are estimated in parts per million accuracy. The theory is demonstrated with an example. In particular, we evaluate whether a dedicated on-chip envelope detector can be used to eliminate the NF test for an LNA.

The deployment of alternative, low-cost RF test methods in industry has been, to date, rather limited. This is due to the potentially impaired ability to identify device pass/fail labels when departing from traditional specification test. By relying on alternative tests, pass/fail labels must be derived indirectly through new test limits defined for the alternative tests, which may incur error in the form of test escapes or yield loss. Clearly, estimating these test metrics as early as possible in the test development process is key to the success of an alternative test approach. In this work, we employ a test metrics estimation technique based on non-parametric kernel density estimation to obtain such early estimates, and, for the first time, demonstrate a real-world case study of test metric estimation efficiency at parts-per-million levels. To achieve this, we employ a set of more than 1 million RF devices fabricated by Texas Instruments, which have been tested with both traditional specification tests as well as alternative, low-cost On-chip RF Built-in Tests, or “ORBiTs”.

A new technique for the estimation of analog parametric test metrics at the design stage is presented in this paper. This technique employs the copulas theory to estimate the distribution between random variables that represent the performances and the test measurements of the circuit under test (CUT). A copulas-based model separates the dependencies between these random variables from their marginal distributions, providing a complete and scale-free description of dependence that is more suitable to be modeled using well-known multivariate parametric laws. The model can be readily used for the generation of an arbitrarily large sample of CUT instances. This sample is thereafter used for estimating parametric test metrics such as defect level (or test escapes) and yield loss. We demonstrate the usefulness of the proposed technique to evaluate a built-in-test technique for a radio frequency low noise amplifier and to set test limits that result in a desired tradeoff between test metrics. In addition, we compare the proposed technique with previous ones that rely on direct density estimation.

This paper discusses a Bayesian fault diagnosis scheme for RF circuits. We use non-idealized spot defect models by taking into account both their resistive and capacitive behavior at the layout level. The likelihoods in the Bayes rule are estimated using nonparametric kernel density estimation. Our case study is an RF low noise amplifier. The diagnosis decisions and the subsequent defect ambiguity analysis are demonstrated using post-layout simulations.

We discuss a fault diagnosis scheme for analog integrated circuits. Our approach is based on an assemblage of learning machines that are trained beforehand to guide us through diagnosis decisions. The central learning machine is a defect filter that distinguishes failing devices due to gross defects (hard faults) from failing devices due to excessive parametric deviations (soft faults). Thus, the defect filter is key in developing a unified hard/soft fault diagnosis approach. Two types of diagnosis can be carried out according to the decision of the defect filter: hard faults are diagnosed using a multi-class classifier, whereas soft faults are diagnosed using inverse regression functions. We show how this approach can be used to single out diagnostic scenarios in an RF low noise amplifier (LNA).

The paper discusses a variety of sensors to enable a built-in test in RF devices. The list of sensors includes dummy circuits, process control monitors, DC probes, an envelope detector, and a current sensor. Dummy circuits and process control monitors are simple circuits that do not tap into the signal path of the RF device. Instead, they monitor the device by virtue of being subject to the same process variations. Their outputs form an alternative measurement pattern which can be mapped to the performances of the device using a typical alternate test flow. The rest of the sensors are physically connected to the RF device, thus they can detect random catastrophic defects within it and, as an auxiliary benefit, they can improve the accuracy in predicting its performances. The degradation that these sensors incur is carefully assessed and the RF device is co-designed with them to correct for the losses. The operation and test efficiency of the sensors is demonstrated for the case of an RF LNA using post-layout simulations.

Alternate RF testing is a very promising candidate for replacing the costly standard specification-based approach. The defect filter in the alternate test flow is a crucial preparatory step for the overall success of alternate test. In this paper, we present a novel nonlinear defect filter based on an estimate of the joint probability density function of the alternate measurements. The construction of the filter does not require a defect dictionary and can accommodate any underlying density without needing any prior knowledge regarding its parametric form.

The high cost of analog circuit testing has sparked off intensified efforts to identify robust and low-cost alternative tests that could effectively replace the standard specification-based tests. Nevertheless, the current practice is still specification-based testing. One of the primary reasons is the lack of tools to evaluate in advance the indirect costs (e.g. parametric test escape and yield loss) associated with alternative tests. To this end, in this paper, we present a method to estimate test escape and yield loss that occur as a result of replacing one costly specification test by one low-cost alternative test. This evaluation is performed at the design or test development stage with parts per million (PPM) accuracy. The method is based on extreme value theory and on a fast simulation technique of extreme events called statistical blockade.

A proof-of-concept hardware neural network for the purpose of analog built-in self-test is presented. The network is reconfigurable into any one-hidden-layer topology within the constraints of the number of inputs and neurons. Analog operation domain of synapses and neurons in conjunction with the digital weight storage allow fast computational time, low power consumption and fast training cycle. The network is trained in the chip-in-the-loop fashion with the simulated annealing-based parallel weight perturbation training algorithm. Its effectiveness in learning how to separate nominal from faulty circuits is investigated on two case studies: a Butterworth filter and an operational amplifier. The results are compared to those of the software neural networks of equivalent topologies and limitations concerning the practical applicability are discussed.

A stand-alone built-in self-test architecture mainly consists of three components: a stimulus generator, measurement acquisition sensors, and a measurement processing mechanism to draw out a straightforward Go/No-Go test decision. In this paper, we discuss the design of a neural network circuit to perform the measurement processing step. In essence, the neural network implements a non-linear classifier which can be trained to map directly sensor-based measurements to the Go/No-Go test decision. The neural network is fabricated as a single chip and is put to the test to recognize faulty from functional RF LNA instances. Its decision is based on the readings of two amplitude detectors that are connected to the input and output ports of the RF LNA. We discuss the learning strategy and the generation of information-rich training sets. It is shown that the hardware neural network has comparable learning capabilities with its software counterpart.

The reduction of analog/RF production test costs calls for the optimization of specification-based tests or their replacement by low-cost ones. A variety of techniques have been proposed in recent years, such as specification-based test ordering and compaction, alternate test to predict the specified performances from simpler measurements, and on-chip circuitry to monitor IC performance while alleviating the complexity of test equipment. Since statistical evidence about test quality can only be gathered from large volume production test data, most innovative test techniques fail to gain acceptance for real products. This is because by the time this evidence could be obtained, most test costs would have already been engaged. At this stage, the change of the test procedure would hardly be acceptable and the modification of the design is no longer possible.

Summary form only given. The complete presentation was not made available for publication as part of the conference proceedings. This forum is organized by the TTTC Student Activities Committee and is designed to give graduate students the opportunity to interact and receive feedback from industrial and academic experts.

This session is a semi-final round of the TTTC 2010 E. J. McCluskey Best Doctoral Thesis Award contest. This contest is organized by the TTTC Student Activities Committee and aims to promote and strengthen the interaction between graduate students and the industrial community, as well as to serve as an opportunity for graduate students to disseminate their research and win recognition for their achievements. The students are offered the chance to present their work in a conference environment to industrial test experts, who will evaluate and comment in terms of novelty, relevance to the state-of-the-art, and advancement of industrial practice.

The production test of analog circuits involves a variety of specification tests. The procedure guarantees outgoing quality levels at the expense of a high cost since it demands long test times and sophisticated test instrumentation. The cost of test is ever increasing as a factor in the overall cost of manufacturing ICs and, as such, it is an area for industry focus, innovation and improvement.

We present a machine learning approach to the problem of RF specification test compaction. The proposed compaction flow relies on a multi-objective genetic algorithm, which searches in the power-set of specification tests to select appropriate subsets, and a classifier, which makes pass/fail decisions based solely on these subsets. The method is demonstrated on production test data from an RF device fabricated by IBM. The results indicate that machine learning can identify intricate correlations between specification tests, which allows us to infer the outcome of all tests from a subset of tests. Thereby, the number of tests that need to be explicitly carried out and the corresponding cost are reduced significantly without adversely impacting test accuracy.

This paper discusses the generation of information-rich, arbitrarily-large synthetic data sets which can be used to (a) efficiently learn tests that correlate a set of low-cost measurements to a set of device performances and (b) grade such tests with parts per million (PPM) accuracy. This is achieved by sampling a non-parametric estimate of the joint probability density function of measurements and performances. Our case study is an ultra-high frequency receiver front-end and the focus of the paper is to learn the mapping between a low-cost test measurement pattern and a single pass/fail test decision which reflects compliance to all performances. The small fraction of devices for which such a test decision is prone to error are identified and retested through standard specification-based test. The mapping can be set to explore thoroughly the tradeoff between test escapes, yield loss, and percentage of retested devices.

Alternate RF testing is a very promising candidate for replacing the costly standard specification-based approach. The defect filter in the alternate test flow is a crucial preparatory step for the overall success of alternate test. In this paper, we present a novel nonlinear defect filter based on an estimate of the joint probability density function of the alternate measurements. The construction of the filter does not require a defect dictionary and can accommodate any underlying density without needing any prior knowledge regarding its parametric form.

In this paper we propose a method for evaluating test measurements for complex circuits that are difficult to simulate. The evaluation aims at estimating test metrics, such as parametric test escape and yield loss, with parts per million (ppm) accuracy. To achieve this, the method combines behavioral modeling, density estimation, and regression. The method is demonstrated for a previously proposed Built-In Self-Test (BIST) technique for ΣΔ Analog-to-Digital Converters (ADC) explaining in detail the derivation of a behavioral model that captures the main nonidealities in the circuit. The estimated test metrics are further analyzed in order to uncover trends in a large device sample that explain the source of erroneous test decisions.

Summary form only given, as follows. This session is the final round of the TTTC 2009 Best Doctoral Thesis Contest. This contest is organized by the TTTC Student Activities Committee for the fifth consecutive year and aims to promote and strengthen the interaction between graduate students and the industrial community, as well as to serve as a process by which student work is exposed to and tested under real-life industrial needs. This is achieved by offering students the chance to present their work in a conference environment to academic and industrial test experts, who will evaluate and comment in terms of novelty and advancement of industrial practice. In the preliminary round of this contest, doctoral students who are expected to graduate in 2009 were invited to submit a one page abstract of their thesis, where they defined the problem and its relevance to industry, described existing industrial practices for solving the problem and explained the proposed methodology and how it advances the theory and/or practice in the particular field. The abstracts were reviewed by a panel of industrial and academic experts and a set of finalists were selected for the final round of the contest. In this final round, during a dedicated session at the IEEE VLSI Test Symposium (VTS’09), each contestant is given a ten minute slot in front of a panel of experts, split equally between oral presentation and Q&A period. The panel of experts will judge the presented doctoral theses with regards to theoretical advancement, industrial relevance and presentation, and the winner of the contest will receive the 2009 TTTC Doctoral Thesis Award during the social event of the Symposium, to which all finalists are invited. The award consists of a certificate, an honorarium and an invitation to submit a paper on the presented work to the IEEE Design & Test magazine.

We present a method that is capable of handling process variations to evaluate analog/RF test measurements at the design stage. The method can readily be used to estimate test metrics, such as parametric test escape and yield loss, with parts per million accuracy, and to fix test limits that satisfy specific tradeoffs between test metrics of interest. Furthermore, it provides a general framework to compare alternative test solutions that are continuously being proposed toward reducing the high cost of specification-based tests. The key idea of the method is to build a statistical model of the circuit under test and the test measurements using nonparametric density estimation. Thereafter, the statistical model can be simulated very fast to generate an arbitrarily large volume of new data. The method is demonstrated for a previously proposed built-in self-test measurement for low-noise amplifiers. The result indicates that the new synthetic data have the exact same structure of data generated by a computationally intensive brute-force Monte Carlo circuit simulation.

We present a general method to evaluate RF built- in self-test (BIST) techniques during the design stage. In particular, the adaptive kernel estimator is used to construct an estimate of the joint probability density function of the performances of the RF device under test and the actual BIST measurements. The density is sampled to generate a large volume of new data, which is subsequently used to estimate the relevant test metrics with parts per million (ppm) accuracy given the BIST limits. Thus, the BIST limits can be set to obtain the desired trade-offs between different test metrics. The proposed method aims to assist designers in comparing RF BIST techniques on the basis of accurately calculated test metrics and to provide information for early BIST refinements, thus reducing the design cycles. The method is demonstrated for a previously published RF BIST technique applied to an LNA.

Unlike the top-down photolithographic CMOS VLSI process, cost-effective bulk fabrication of nanodevices calls for a bottom-up approach, generally called self-assembly. Self- assembly, however, inherently lends itself to innate disparities in the structure of nominally identical nanodevices and, consequently, wide inter-device variance in their functionality. As a result, nanodevice characterization and testing calls for a slow and tedious procedure involving a large number of measurements. In this work, we discuss a statistical approach which learns measurement correlations from a small set of fully characterized nanodevices and utilizes the extracted knowledge to simplify the process for the rest of the nanodevices. More specifically, we employ various machine-learning methods which rely on a small subset of measurements to (i) predict the performances of a fabricated nanodevice, (ii) decide whether a nanodevice passes or fails a given set of specifications, and (iii) bin a nanodevice with regards to several sets of increasingly strict specifications. The proposed methods are demonstrated and their effectiveness is assessed, within the context of nanowire-based chemical sensing, using a set of fabricated and fully characterized nanowires.

Machine-learning-based test methods for analog/RF devices have been the subject of intense investigation over the last decade. However, despite the significant cost benefits that these methods promise, they have seen a limited success in replacing the traditional specification testing, mainly due to the incurred test error which, albeit small, cannot meet industrial standards. To address this problem, we introduce a neural system that is trained not only to predict the pass/fail labels of devices based on a set of low-cost measurements, as aimed by the previous machine-learning-based test methods, but also to assess the confidence in this prediction. Devices for which this confidence is insufficient are then retested through the more expensive specification testing in order to reach an accurate test decision. Thus, this two-tier test approach sustains the high accuracy of specification testing while leveraging the low cost of machine-learning-based testing. In addition, by varying the desired level of confidence, it enables the exploration of the tradeoff between test cost and test accuracy and facilitates the development of cost-effective test plans. We discuss the structure and the training algorithm of an ontogenic neural network which is embodied in the neural system in the first tier, as well as the extraction of appropriate measurements such that only a small fraction of devices are funneled to the second tier. The proposed test-error-moderation method is demonstrated on a switched-capacitor filter and an ultrahigh-frequency receiver front end.

The authors present a case study that employs production test data from an RF device to assess the effectiveness of four different methods in predicting the pass/fail labels of fabricated devices based on a subset of performances and, thereby, in decreasing test cost. The device employed is a zero-IF down-converter for cell-phone applications and the four methods range from a sample maximum-cover algorithm to an advanced ontogenic neural network. The results indicate that a subset of non-RF performances suffice to predict correctly the pass/fail label for the vast majority of the devices and that the addition of a few select RF performances holds great potential for reducing misprediction to industrially acceptable levels. Based on these results, the authors then discuss enhancements and experiments that will further corroborate the utility of these methods within the cost realities of analog/RF production testing.

Numerous machine-learning-based test methodologies have been proposed in recent years as a fast alternative to the standard functional testing of mixed-signal/RF integrated circuits. While the test error probability of these methods is rather low, it is still considered prohibitive for accurate production testing. In this paper, we demonstrate how to minimize this test error probability and, thus, how to bridge the accuracy of functional and machine-learning-based test methods. The underlying idea is to measure the confidence of the machine-learning-based test decision and retest the small fraction of circuits for which this confidence is low via standard functional test. Through this approach, the majority of circuits are tested using fast machine-learning-based tests, which, nevertheless, are equivalent to the standard functional ones with regards to test error probability. By varying the acceptable confidence level, the proposed method enables exploration of the trade-off between test time and test accuracy

This paper presents a novel methodology for concurrent error detection in linear analog circuits. The error-detection circuit monitors the input and some observable internal nodes of the examined circuit and generates an estimate of its output. The estimate coincides with the output in error-free operation, while in the presence of errors, it diverges. Thus, concurrent error detection is performed by comparing the two signals through an analog comparator. In essence, the error-detection circuit operates as a duplicate of the examined circuit, yet it is smaller, in general, and never exceeds the size of an actual duplicate. The proposed methodology is demonstrated on three analog filters.

We develop a neural network that learns to separate the nominal from the faulty instances of a circuit in a measurement space. We demonstrate that the required separation boundaries are, in general, non-linear. Unlike previous solutions which draw hyperplanes, our network is capable of drawing the necessary non-linear hypersurfaces. The hypersurfaces translate to test criteria that are strongly correlated to functional tests. A feature selection algorithm interacts with the network to identify a discriminative low-dimensional measurement space.

We discuss the design of a neural system that learns to separate nominal from faulty instances of an analog circuit in a low dimensional measurement space. The key novelty of the proposed system is that it successively establishes a separation hypersurface of order that adapts to the intrinsic complexity of the problem. Thus, it performs excellent classification even in the presence of complex distributions. The test criterion for classifying a circuit is simply the location of its measurement pattern with respect to the separation hypersurface. Despite its simplicity, this criterion is, by construction, strongly correlated to the performance parameters of the circuit and does not rely on fault models.

A neural classifier that learns to separate the nominal from the faulty instances of a circuit in a measurement space is developed. Experimental evidence, which demonstrates that the required separation boundaries are, in general, nonlinear, is presented. Unlike previous solutions that build hyperplanes, the proposed classifier is capable of drawing nonlinear hypersurfaces. A new circuit instance is classified through a simple test, which examines the location of its measurement pattern with respect to these hypersurfaces. The classifier is trained through an algorithm that probably converges to the optimal separation boundary. Additionally, a feature selection algorithm interacts with the classifier to identify a discriminative low-dimensional measurement vector. Despite employing only a few measurements, the test criteria established by the neural classifier are strongly correlated to the performance parameters of the circuit and do not rely on a presumed fault model.

We discuss the design of a novel analog checker that monitors two duplicate signals and provides a digital error indication when their absolute difference is unacceptably large. The key feature of the proposed checker is that it establishes a test criterion that is dynamically adapted to the magnitude of its input signals. We demonstrate that, when this checker is utilized in concurrent error detection, the probability of both false negatives and false positives is diminished. In contrast, checkers implementing a static test criterion may only be tuned to achieve efficiently one of the aforementioned objectives. Likewise, when the proposed checker is employed for off-line test purposes, it results simultaneously in both high yield and high fault coverage.

We present a novel analog checker that adjusts dynamically the error threshold to the magnitude of its input signals. We demonstrate that this property is crucial for accurate concurrent error detection in analog circuits. Dynamic error threshold adjustment is achieved by regulating the bias point of the output stage inverters of the checker, which provide a digital indication of potential errors in the circuit under test. We discuss the theoretical foundation and we present simulations that validate the underlying principle of the design. As compared to previous solutions, the proposed checker reduces the incurred overhead, while significantly enhancing the quality of concurrent error detection.