Demo Data from VLDB 2026 / reviewers in the wild / expert
Miguel A. Marin
dblp:11/416
· DBLP profile ↗
4ranked-venue papers
1as first author
0since 2021 · last 1992
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2Applied, interdisciplinary, general and emerging computing · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Artificial intelligence
1 paper |
Knowledge representation and reasoning · 100% | |
| Interdisciplinary, comprehensive, and emerging computing
1 paper |
Energy systems and smart grids · 100% | |
| Theoretical computer science
2 papers |
Logic in computer science · 88% Automata and formal languages · 12% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 100% |
Topics — the 9 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Knowledge, reasoning and agents › Knowledge representation and reasoning
expert systems |
0.0 | 1 | 1992 | Expert systems in transmission planning · Proc. IEEE 1992 |
Knowledge, reasoning and agents › Knowledge representation and reasoning
knowledge-based systems |
0.0 | 1 | 1992 | Expert systems in transmission planning · Proc. IEEE 1992 |
Energy systems and smart grids › power system planning and operation
power system planning |
0.0 | 1 | 1992 | Expert systems in transmission planning · Proc. IEEE 1992 |
Energy systems and smart grids
power system operation |
0.0 | 1 | 1992 | Expert systems in transmission planning · Proc. IEEE 1992 |
Electronic design automation
logic synthesis |
0.0 | 2 | 1977 | An Approach to Unified Methodology of Combinational Switching Circuits · IEEE Trans. Computers 1977 A Computer Algorithm for the Synthesis of Memoryless Logic Circuits · IEEE Trans. Computers 1974 |
Logic in computer science › algebraic logic › boolean algebra
boolean equation solving |
0.0 | 2 | 1977 | An Approach to Unified Methodology of Combinational Switching Circuits · IEEE Trans. Computers 1977 A Computer Algorithm for the Synthesis of Memoryless Logic Circuits · IEEE Trans. Computers 1974 |
Electronic design automation › logic synthesis
combinational logic synthesis |
0.0 | 1 | 1974 | A Computer Algorithm for the Synthesis of Memoryless Logic Circuits · IEEE Trans. Computers 1974 |
Logic in computer science › algebraic logic › boolean algebra › boolean function representation
functional decomposition |
0.0 | 1 | 1974 | A Computer Algorithm for the Synthesis of Memoryless Logic Circuits · IEEE Trans. Computers 1974 |
Automata and formal languages › finite automata › sequential machines
mealy machine |
0.0 | 1 | 1977 | An Approach to Unified Methodology of Combinational Switching Circuits · IEEE Trans. Computers 1977 |
Methods — techniques the papers use, named apart from their topics
knowledge engineering · 0.0functional decomposition · 0.0constraint equations · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1992 | Expert systems in transmission planningabstractThe state of the field of expert systems and knowledge engineering in transmission planning is reviewed. A detailed analysis of the goals, definition, requirements and methodology of transmission planning is presented. Potential benefits of knowledge-based applications in transmission planning are reviewed. This is followed by a thorough review of the area broken down into subareas or important related topics. The conclusions offer a number of suggestions for possible future research and development. Finally, a detailed bibliography divided into subareas is presented.> Francisco D. Galiana, Donald T. McGillis, Miguel A. Marin |
Proc. IEEE | 3 |
| 1977 | An Approach to Unified Methodology of Combinational Switching CircuitsabstractA methodology based on the theory of Boolean equations has been developed which permits a unified approach to the analysis and synthesis of combinational logic circuits. The type of circuits covered by the approach includes both the classical loopless combinational networks as well as those that contain closed feedback loops and thus have internally a sequential character. To that end, a general multiple-output circuit represented by a Mealy-type machine is studied using characteristic equations (functions) that describe its internal structure. It is shown how behavioral properties of the circuit are reflected through the sosutions of these equations. Moreover, it is demonstrated that a multiple-output incompletely specified switching function is reaeized if a ≤ relation is satisfied between the corresponding charchteristic functions. This leads to a new unified outlook on functional decomposition as used in modular synthesis procedures. Although the building modules are allowed to be sequential circuits, it is shown under which conditions the feedback loops are redundant with respect to the realization of a given output characteristic function, and thus the existence conditions of nondegenerate combinational circuits with loops are stated. Eduard Cerny, Miguel A. Marin |
IEEE Trans. Computers | 2 |
| 1974 | A Computer Algorithm for the Synthesis of Memoryless Logic CircuitsabstractA method has been investigated for the synthesis of memoryless logical networks using a restricted repertoire of functional modules. The method is based on the reduced general solution to a generalized system of Boolean equations (BE) as applied to the decomposition of Boolean functions. The aim of the synthesis is to obtain the most constrained circuit having at most two levels of gating. The constraints take the form of single input variables or constant logic levels applied to the inputs of the first level gate. This is achieved by assembling a set of constraint equations which are then a part of the generalized system of BE. The method is then tested on some synthesis examples of single and multiple output functions in terms of the NAND and (WOS) modules. Eduard Cerny, Miguel A. Marin |
IEEE Trans. Computers | 2 |
| 1969 | Synthesis of TANT networks using a Boolean analyserabstractThe automated synthesis of TANT combinational networks (Three-level AND-NOT networks with True inputs) is studied using the advantages of Svoboda Boolean Analyzer (SBA) (see Svoboda, 1968). The synthesis procedure consists of (i) calculating the ordinary prime implicants of the given function f using operation Mode I of SBA, (ii) calculation of all generalised prime implicants of f by solving a system of Boolean equations (operation Mode II), (iii) solution of a covering problem using a special Petrick function and operation Mode I of the SBA. The synthesis procedure yields a TANT network containing a minimum number of AND-NOT elements. FORTRAN IV programs have been developed which implement the proposed synthesis method; however, the SBA hardware unit, when available, will prove an efficiency factor in processing time of approximately 104. Miguel A. Marin |
Comput. J. | 1 |