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Tadashi Ae

dblp:11/4178 · DBLP profile ↗
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15ranked-venue papers
7as first author
0since 2021 · last 1998
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Theory of computation · 7 · 2 first-authorSystems, architecture and hardware · 3 · 1 first-authorSoftware engineering, systems software and programming languages · 2Applied, interdisciplinary, general and emerging computing · 2 · 2 first-authorArtificial intelligence and machine learning · 1 · 1 first-authorDatabases, data management, data science and information retrieval · 1Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
5 papers
Distributed systems · 70% Performance modeling and evaluation · 12% Hardware accelerators and domain-specific architectures · 8%

Topics — the 12 heaviest of 13, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Distributed systems › quorum systems
coterie
0.011993
Availability of k-Coterie · IEEE Trans. Computers 1993
Distributed systems › mutual exclusion
distributed mutual exclusion
0.011993
Availability of k-Coterie · IEEE Trans. Computers 1993
Distributed systems
fault tolerance
0.011993
Availability of k-Coterie · IEEE Trans. Computers 1993
Distributed systems › mutual exclusion
k-mutual exclusion
0.011993
Availability of k-Coterie · IEEE Trans. Computers 1993
Performance modeling and evaluation › performance prediction
response time estimation
0.011987
A Response Time Estimation of Real-Time Networks · RTSS 1987
Performance modeling and evaluation
workload characterization
0.011982
Experimentation and Analysis of Multiprocessor Systems · RTSS 1982
Integrated circuit design › 3d integration
3D VLSI
0.011987
A Template Matching Algorithm Using Optically-Connected 3-D VLSI Architecture · ISCA 1987
Interconnection networks and networks-on-chip
optical interconnection networks
0.011987
A Template Matching Algorithm Using Optically-Connected 3-D VLSI Architecture · ISCA 1987
Embedded and real-time systems › real-time communication
real-time networks
0.011987
A Response Time Estimation of Real-Time Networks · RTSS 1987
Parallel and multicore computing
multiprocessor system
0.011982
Experimentation and Analysis of Multiprocessor Systems · RTSS 1982
Electronic design automation
circuit synthesis
0.011973
A Method of Synthesis and Decomposition of Autonomous Linear Sequential Circuits · Inf. Control. 1973
Integrated circuit design
digital circuit design
0.011973
A Method of Synthesis and Decomposition of Autonomous Linear Sequential Circuits · Inf. Control. 1973

Methods — techniques the papers use, named apart from their topics

probabilistic reliability analysis · 0.0simulation · 0.0algebraic formulation · 0.0linear algebra over finite fields · 0.0
YearPublicationVenuePosition
1998 Hardware of structured brain computer
abstract
We have proposed a two-level architecture for brain computing, where two levels are introduced for processing of meta-symbol. At Level 1 a conventional pattern recognition is performed, where neural computation is included, and its output gives the meta-symbol which is a symbol enlarged from a symbol to a kind of pattern. At Level 2 an algorithm acquisition is made by using a state machine for abstract states (which is a meta-symbol expression). We are also developing the VLSI chips at each level for the structured brain computer (SBC) version 1.0. To explain SEC we introduce the brain computing and the artificial memory system as well as the hardware of SBC.
Tadashi Ae, Keiichi Sakai, Hiroyuki Araki, Naoya Honda
KES (3)1
1995 A construction of neural-net based AI systems
abstract
The paper investigates the integration of the neural network technique and traditional AI techniques towards the realization of a real-time neuron-based AI architecture. As the first step of our project, we propose a neural network based AI system, called NAI. NAI is a kind of real-time CBR (case-based reasoning) system in which the WTA (winner-take-all) type neural network is embedded for supporting the real-time classification and retrieval of a massive case-base. For flexible learning with the WTA neural network, two learning algorithms (supervised and unsupervised) have been developed on the basis of the LVQ1 and self-organizing learning algorithms.
Manabu Kawada, Tadashi Ae
ICECCS3
1994 A Distributed k-Mutual Exclusion Algorithm Using k-Coterie
Hirotsugu Kakugawa, Satoshi Fujita, Masafumi Yamashita, Tadashi Ae
Inf. Process. Lett.4
1993 Optimal Group Gossiping in Hypercubes Under Wormhole Routing Model
Satoshi Fujita, Masafumi Yamashita, Tadashi Ae
ISAAC3
1993 Availability of k-Coterie
abstract
The distributed k-mutual-exclusion problem (k-mutex problem) is the problem of guaranteeing that at most k processes at a time can enter a critical section at a time in a distribution system. A method proposed for the solution of the distributed mutual exclusion problem (i.e., 1-mutex problem) by D. Barbara and H. Garcia-Molina (1987) is an extension of majority consensus and uses coteries. The goodness of coterie-based 1-mutex algorithm strongly depends on the availability of coterie, and it has been shown that majority coterie is optimal in this sense, provided that: the network topology is a complete graph, the links never fail, and p, the reliability of the process, is at least 1/2. The concept of a k-coterie, an extension of a coterie, is introduced for solving the k-mutex problem, and lower and upper bounds are derived on the reliability p for k-majority coterie, a natural extension of majority coterie, to be optimal, under conditions (1)-(3). For example, when k=3, p must be greater than 0.994 for k-majority coterie to be optimal.>
Hirotsugu Kakugawa, Satoshi Fujita, Masafumi Yamashita, Tadashi Ae
IEEE Trans. Computers4
1989 Programmable Real-Time Scheduler Using a Neurocomputer
Tadashi Ae, Reiji Aibara
Real Time Syst.1
1987 A Template Matching Algorithm Using Optically-Connected 3-D VLSI Architecture
abstract
Three-dimensional VLSI (in short, 3-D VLSI) is a new device technology that is expected to realize high performance systems. In this paper, we propose an image processing architecture based on 3-D VLSI consisting of optically-connected layers. Since the optical inter-layer connection seems to have some of useful functions due to isotropic radiation of the light, we algebraicly formulate them as the picture processing operators. Moreover, we show that the operators are available for applications such as template matching. The availability of a proposed template matching algorithm is verified by simulation.
Satoshi Fujita, Reiji Aibara, Masafumi Yamashita, Tadashi Ae
ISCA4
1987 A Response Time Estimation of Real-Time Networks
Tadashi Ae, Masafumi Yamashita, Hiroshi Matsumoto
RTSS1
1983 On the NP-hardness of edge-deletion and -contraction problems
Toshimasa Watanabe, Tadashi Ae, Akira Nakamura
Discret. Appl. Math.2
1982 Experimentation and Analysis of Multiprocessor Systems
Tadashi Ae, Reiji Aibara
RTSS1
1981 On the removal of forbidden graphs by edge-deletion or by edge-contraction
Toshimasa Watanabe, Tadashi Ae, Akira Nakamura
Discret. Appl. Math.2
1980 Computer Graphics in Multiple Microprocessor System
abstract
In this paper we propose a method to implement the moving patterns which are consecutively related in a small computer system. Suppose that the patterns are constructed of many block elements. A pattern is derived by the operation ( such as AND, OR, EXOR, MOVE, ZOOM, ROTATE,. .. ), with another pattern if it is required as operand. The parallel execution on a multiple microprocessor system is also discussed.
Tadashi Ae, Koichi Takahashi, Haruyoshi Chiba, Tsurumi Ito
Eurographics1
1979 One-Way Simple Multihead Finite Automata
Katsushi Inoue, Itsuo Takanami, Akira Nakamura, Tadashi Ae
Theor. Comput. Sci.4
1977 Direct or Cascade Product of Pushdown Automata
Tadashi Ae
J. Comput. Syst. Sci.1
1973 A Method of Synthesis and Decomposition of Autonomous Linear Sequential Circuits
Tadashi Ae, Noriyoshi Yoshida
Inf. Control.1