This work provides an analysis of dual-factor authentication protocol for securing low-power medical devices. The dual-factor protocol incorporates voluntary physical action-based authentication in addition to traditional cryptographic methods for adding an extra layer of security. Along with touch signals, we propose and analyze the use of electromyographic (EMG) signals obtained from hand gestures for the second factor authentication. We demonstrate the feasibility of touch and EMG signals for dual-factor authentication by prototyping the medical device using off-the-shelf components. We also develop energy models for all these protocols, and analyze their overheads compared to traditional single-factor cryptographic authentication.

In the fast growing world of the Internet of Things (IoT), security has become a major concern. Datagram Transport Layer Security (DTLS) is considered to be one of the most suited protocols for securing the IoT. However, computation and communication overheads make it very expensive to implement DTLS on resource-constrained IoT sensor nodes. In this work, we profile the energy costs of DTLS 1.3, using experimental models for cryptographic computations and radio-frequency (RF) communications. Based on this analysis, we present eeDTLS, a low-energy variant of DTLS, that provides the same security strength as DTLS, but has lower energy requirements. By employing a combination of packet size reduction and optimized handshake computations, eeDTLS can provide up to 45% energy savings in a typical IoT use case. eeDTLS can be implemented in conjunction with any low-energy IoT RF protocol, and the proposed energy models and protocol optimizations can also be used to improve the energy efficiency of custom IoT security architectures.

Serial memories built from charge-coupled devices (CCD's) offer an opportunity for minimizing latency times not available with the more conventional drum and disk (serial) memory units. Let r be the ratio of the maximum to the minimum clocking rates for the CCD memory. We show that in many practical situations the average latency can be reduced from 1/2 to 1/(1 + √r) of a revolution time if the optimal clocking strategy is used when the CCD is idle.

The analysis in this paper shows a multiprocessor like C.mmp to have a factor of three to four cost/performance advantage over uniprocessor systems such as the PDP-10 when implementations using similar technologies are considered. This comparison is shown to be very sensitive to memory prices and considerable attention is given to normalizing memory costs between C.mmp and the PDP-10.

The structure of microprogrammed processors is largely determined by the state of (semiconductor) technology and the requirements of the task of emulation. We discuss the impact of LSI components on microprogrammable processors and in particular, the effect of large memory arrays, LSI microprocessors (bit-slices), programmable logic arrays, and high-speed shifters.

The modehng and analysis of drum-hke storage units are discussed.Two common forms of drum organizations and two common scheduhng dlsclphnes are considered the file drum and the paging drum; first-m-first-out (FIFO) scheduh ~g and shortest-latency-time-first (SLTF) scheduhngThe modehng of the I/O requests to the drum is an important aspect of this analysis Measurements are presented to mdmate that ~t ~s reahstm to model requests for records, or blocks of mformatron to a file drum, as requests that have starting addresses umformly dmtrlbuted around the circumference of the drum and transfer times that are exponentially distributed with a mean of ½ to of a drum revolution The arrival of I/O requests is first assumed to be a Polsson process and then generalized to the case of a computer system with a finite degree of multlprogrammmg An exact analyms of all the models except the SLTF file drum ts presented; m th~s case the complexity of the drum orgamzatlon has forced us to accept an approximate analysis In order to examine the error introduced into the analysis of the SLTF file drum by our approximations, the results of the analytm models are compared to a simulatmn model of the SLTF file drum.Comparisons of the models indicate that the scheduhng dlsclphne is more important to performance than drum orgamzation

This paper discusses various analytical techniques for studying the extent of memory interference in a multiprocessor system with a crosspoint switch for processor-memory communication. Processor behavior is simplified to an ordered sequence of a memory request followed by an interval of processing time. The system is assumed to be bus bound; in other words, by the time the processor-memory bus completes servicing a processor's request the processor is ready to initiate another request and the memory module is ready to accept another request. The techniques discussed include discrete and continuous time Markov chain models as well as several approximate analytic methods.

This paper describes the architecture of Computer Modules, or CMs. They are large digital modules of about minicomputer complexity that are specifically designed to take advantage of the rapidly advancing semiconductor technology. These modules are intended to be interconnected into systems that implement a wide range of computational structures. The main features of a CM include a small processor as the primary control element and memory distributed among the CMs in the system rather than centralized into memory modules as in current multiprocessors. CMs are interconnected into a network via buses that each have their own virtual address space to facilitate efficient inter-module memory sharing. This paper includes an ISP description of the address translation mechanisms as well as a discussion of several important implementation issues such as the avoidance of deadlocks in CM networks and the width of the inter-CM buses.

In a multiprogramming, virtual-memory computing system, many processes compete simultaneously for system resources, which include CPU's, main memory page frames, and the transmission capacity of the paging drum. (We define a “process” here as a program with its own virtual memory, requiring an allocation of real memory and a CPU in order to execute). This paper studies ways of allocating resources to processes in order to maximize throughput in systems which are not CPU-bound.

This article investigates the application of minimal-total-processing-time (MTPT) scheduling disciplines to rotating storage units when random arrival of requests is allowed. Fixed-head drum and moving-head disk storage units are considered and particular emphasis is placed on the relative merits of the MTPT scheduling discipline with respect to the shortest-latency-time-first (SLTF) scheduling discipline. The results of the simulation studies presented show that neither scheduling discipline is unconditionally superior to the other. For most fixed-head drum applications the SLTF discipline is preferable to MTPT, but for intra-cylinder disk scheduling the MTPT discipline offers a distinct advantage over the SLTF discipline. An implementation of the MTPT scheduling discipline is discussed and the computational requirements of the algorithm are shown to be comparable to SLTF algorithms. In both cases, the sorting procedure is the most time consuming phase of the algorithm.

Suppose a set of N records must be read or written from a drum, fixed-head disk, or similar storage unit of a computer system. The records vary in length and are arbitrarily located on the surface of the drum. The problem considered here is to find an algorithm that schedules the processing of these records with the minimal total amount of rotational latency (access time), taking into account the current position of the drum. This problem is a special case of the traveling salesman problem. The algorithm that is developed has the attractive property of exhibiting a computational complexity on the order of N log N.