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Michael Demjanenko

dblp:11/4946 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1990
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 56% Hardware reliability and fault tolerance · 44%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance
defect tolerance
0.011990
Yield enhancement of field programmable logic arrays by inherent component redundancy · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990
Electronic design automation › logic synthesis
programmable logic array
0.011990
Yield enhancement of field programmable logic arrays by inherent component redundancy · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990
Hardware reliability and fault tolerance › redundancy
redundancy-based repair
0.011990
Yield enhancement of field programmable logic arrays by inherent component redundancy · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990
Electronic design automation › design for manufacturability › design for yield
yield enhancement
0.011990
Yield enhancement of field programmable logic arrays by inherent component redundancy · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990
Electronic design automation › hardware verification and test
fault diagnosis
0.011990
Yield enhancement of field programmable logic arrays by inherent component redundancy · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990
Electronic design automation
hardware verification and test
0.011990
Yield enhancement of field programmable logic arrays by inherent component redundancy · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990

Methods — techniques the papers use, named apart from their topics

graph-theoretic formulation · 0.0bipartite matching · 0.0
YearPublicationVenuePosition
1990 Yield enhancement of field programmable logic arrays by inherent component redundancy
abstract
A complete technique that does not use any additional components for enhancing the yield of field-programmable logic arrays (FPLAs) is presented. In this approach, the inherent sparsity (absence of devices at crosspoints) of programmable logic arrays (PLAs) is utilized to mask certain types of manufacturing defects within the unprogrammed FPLAs, thus reclaiming chips which are otherwise discarded. Two categories of faults (called type 1 and type 2) are considered. Type-1 faults, which can be diagnosed a priori, are considered first. After diagnosing type 1 faults, the mask can be reconfigured around the faulty crosspoints. A streamlined bipartite matching algorithm is presented to enhance the speed of this reconfiguration. The uniqueness of the approach is that the programming of an FPLA is formulated as a graph theoretic problem for which a polynomial time solution exists. Type-2 faults in general cannot be diagnosed a priori. Therefore, a dynamic technique is presented for the repair of type-2 faults. Unused product lines of the FPLA are utilized for the repair. With a sufficient number of excess product lines, it is shown that a defective FPLA is guaranteed to be rendered usable. A probability measure for the usability of defective FPLA is obtained both with and without the implementation of this technique. Computer studies have shown that FPLAs with even a large number of defects can be successfully repaired, thereby increasing the yield.>
Michael Demjanenko, Shambhu J. Upadhyaya
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1988 Dynamic Techniques for Yield Enhancement of Field Programmable Logic Arrays
abstract
Two techniques are presented to increase the effective yield of field programmable logic arrays (FPLAs). In the first technique, a reconfiguration scheme is proposed to dynamically alter the product-term allocation of the mask PLA onto the product lines of the raw FPLA once a type-two fault is diagnosed. This technique does not require any extra product lines to obtain a usable destination FPLA. The second technique utilizes the often unused product lines within the FPLA. It is shown that once an error is detected during the programming procedure, a product line can always be desensitized from the rest of the FPLA. The intended product term is then simply reprogrammed onto one of the extra product lines.>
Michael Demjanenko, Shambhu J. Upadhyaya
ITC1