This paper presents a practicable scheme for building a high-frequency direct-digitizing transmitter. The transmitter uses a simple look-up table to generate a binary output stream, which is then filtered to produce a radiated signal, so that there is no need for precise digital-to-analog converters. The data in the look-up table is produced by a new constrained-list-decoding algorithm operating over the real alphabet. The transmitter can only be a modulator, or a combined encoder and modulator. The technology presented in this paper supports the generation of RF signals for commercial applications. The 10-Gbit DSP architectures currently produced for ethernet, for e.g., can be used directly to transmit these binary sequences. The paper concludes with spectra and error vector magnitude measurements for Gaussian minimum shift keying (GMSK) and quadrature phase shift keying (QPSK) with frequencies over 10 GHz.

This paper studies the use of structures based on error correcting codes to achieve secrecy rather than error control. In many cases, however, the same code can achieve both error control and secrecy. It describes an optimal construction for combining multiple semisecure channels, e.g., a bundle of fiber-optic cables or reels of tape sent by independent couriers, into a single channel with much higher security. It shows how mixing and scrambling functions formed from error correcting codes can be used to enhance the security of trunked communications circuits and conventional cryptographic systems which depend, for their security, on unproven assertions about computational difficulty.

Hard limiters, which are nearly identical to level crossing detectors or zero crossing detectors, are an integral part of many communications systems, of devices for characterizing precision oscillators, and of analog-to-digital converters. The purpose of a hard limiter is to divide the continuous range of an analog input signal into two regions and to provide a digital output indicating the region in which the signal is. This digital output must, by definition, have an extremely short transition time. A hard limiter is thus a slope amplifier, since a slowly varying input must produce a very rapidly varying output. Noise in the amplifiers causes the output transition to be jarred from its correct position producing jitter in the output. This paper presents the analysis and details the design of very low jitter hard limiters. Their immediate application is to the measurement of high stability signal sources and to deep space communication and ranging; the results, however, are easily adapted to many other purposes such as waveform digitization. One of the devices described has been built. Its performance agrees closely with theory and is vastly superior to that of conventional instrumentation.

In Reed-Solomon codes and all other maximum distance separable codes there is an intrinsic relationship between the size of the symbols in a codeword and the length of the codeword. Increasing the number of symbols in a codeword to improve the efficiency of the coding system thus requires using larger symbols. However, long Reed-Solomon codes are difficult to implement and many communications or storage systems cannot easily accommodate an increased symbol size, e.g., M-ary FSK and photon counting pulse position modulation demand a fixed symbol size. This paper describes a technique for sharing redundancy among many different Reed-Solomon codewords to achieve the efficiency attainable in long Reed-Solomon codes without increasing the symbol size. The paper presents techniques both for calculating the performance of these new codes and for determining their encoder and decoder complexities. These complexities are usually substantially lower than conventional Reed-Solomon codes of similar performance.

The loss in quantizing coded symbols in the additive white Gaussian noise (AWGN) channel with binary phase-shift keying (BPSK) or quadrature phase-shift keying (QPSK) modulation is discussed. A quantization scheme and branch metric calculation method are presented. For the uniformly quantized AWGN channel, cutoff rate is used to determine the step size and the smallest number of quantization bits needed for a given bit-signal-to-noise ratio (E/sub b//N/sub 0/) loss. A nine-level quantizer is presented, along with 3-b branch metrics for a rate-1/2 code, which causes an E/sub b//N/sub 0/ loss of only 0.14 dB. These results also apply to soft-decision decoding of block codes. A tight upper bound is derived for the range of path metrics in a Viterbi decoder. The calculations are verified by simulations of several convolutional codes, including the memory-14, rate-1/4 or -1/6 codes used by the big Viterbi decoders at JPL.>

The deBruijn graph B n is the state diagram for an n -stage binary shift register. It has 2 n vertices and 2 n + 1 edges. In this papers, it is shown that B n can be built by appropriately “wiring together“ (i.e., connecting together with extra edges) many isomorphic copies of a fixed graph, which is called a building block for B n . The efficiency of such a building block is refined as the fraction of the edges of B n which are present in the copies of the building block. It is then shown, among other things, that for any α < 1, there exists a graph G which is a building block for B n of efficiency > α for all sufficiently large n . These results are illustrated by describing how a special hierarchical family of building blocks has been used to construct a very large Viterbi decoder (whose floorplan is the graph B 13 ) which will be used on NASA's Galileo mission.