Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Javier J. Sieiro

dblp:11/8030 · also Javier Sieiro Córdoba · DBLP profile ↗
← Back
8ranked-venue papers
0as first author
0since 2021 · last 2020
0000-0001-9545-5347ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 8

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Electronic design automation · 68% Integrated circuit design · 32%
Theoretical computer science
2 papers
Mathematical optimization · 100%

Topics — the 9 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
analog and RF circuit synthesis
0.932020
A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017
Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014
Integrated circuit design
radio-frequency circuit design
0.632019
An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017
Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014
Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019
Electronic design automation
design optimization
0.412020
A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Electronic design automation
multi-objective optimization
0.412020
A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Electronic design automation › analog circuit design automation
analog layout synthesis
0.412019
Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019
Integrated circuit design › radio-frequency circuit design
low noise amplifier
0.312017
An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017
Mathematical optimization
multi-objective optimization
0.122017
An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017
Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014
Integrated circuit design › radio-frequency circuit design
radio frequency integrated circuits
0.112020
A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Mathematical optimization › multi-objective optimization
pareto front
0.112017
An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017

Methods — techniques the papers use, named apart from their topics

multi-objective optimization · 1.8electromagnetic simulation · 1.8pareto-optimal front · 0.6electrical simulation · 0.4evolutionary algorithm · 0.4
YearPublicationVenuePosition
2020 A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems
abstract
In recent years there has been a growing interest in electronic design automation methodologies for the optimization-based design of radio frequency (RF) circuits and systems. While for simple circuits several successful methodologies have been proposed, these very same methodologies exhibit significant deficiencies when the complexity of the circuit is increased. The majority of the published methodologies that can tackle RF systems are either based on high-level system specification tools or use models to estimate the system performances. Hence, such approaches do not usually provide the desired accuracy for RF systems. In this paper, a methodology based on hierarchical multilevel bottom-up design approaches is presented, where multiobjective optimization algorithms are used to design an entire RF system from the passive component level up to the system level. Furthermore, each level of the hierarchy is simulated with the highest accuracy possible: electromagnetic simulation accuracy at device-level and electrical simulations at circuit/system-level.
Fábio Passos, Elisenda Roca, Javier J. Sieiro, Rafaella Fiorelli, Rafael Castro-López, José María López-Villegas, Francisco V. Fernández 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
2019 Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop
abstract
In this paper, an analysis of the methodologies proposed in the past years to automate the synthesis of radio-frequency (RF) integrated circuit blocks is presented. In the light of this analysis, and to avoid nonsystematic iterations between sizing and layout design steps, a multiobjective optimization-based layout-aware sizing approach with preoptimized integrated inductor(s) design space is proposed. An automatic layout generation from netlist to ready-to-fabricate prototype is carried in-the-loop for each tentative sizing solution using an RF-specific module generator, template-based placer and evolutionary multinet router with preoptimized interconnect widths. The proposed approach exploits the full capabilities of the most established computer-aided design tools for RF design available nowadays, i.e., RF circuit simulator as performance evaluator, electromagnetic simulator for inductor characterization, and layout extractor to determine the complete circuit layout parasitics. Experiments are conducted over a widely used circuit in the RF context, showing the advantages of performing complete layout-aware sizing optimization from the very initial stages of the design process.
Ricardo Martins 0003, Nuno Lourenço 0003, Fábio Passos, Ricardo Povoa, António Canelas, Elisenda Roca, Rafael Castro-López, Javier J. Sieiro, Francisco V. Fernández 0001, Nuno Horta
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.8
2018 Quasi-static PEEC planar solver using a weighted combination of 2D and 3D analytical Green's functions and a predictive meshing generator
Saiyd Ahyoune, Javier J. Sieiro, Tomás Carrasco Carrillo, Neus Vidal, José María López-Villegas, Elisenda Roca, Francisco V. Fernández 0001
Integr.2
2017 An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors
abstract
A new design methodology for radiofrequency circuits is presented that includes electromagnetic (EM) simulation of the inductors into the optimization flow. This is achieved by previously generating the Pareto-optimal front (POF) of the inductors using EM simulation. Inductors are selected from the Pareto front and their S-parameter matrix is included in the circuit netlist that is simulated using an RF simulator. Generating the EM-simulated POF of inductors is computationally expensive, but once generated, it can be used for any circuit design. The methodology is illustrated both for a singleobjective and a multiobjective optimization of a low noise amplifier.
Reinier Gonzalez-Echevarria, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández 0001, Javier J. Sieiro, José María López-Villegas, Neus Vidal
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.5
2016 Introduction to the special issue on Radio Frequency Integrated Circuits (RFIC) design techniques
Elisenda Roca, Javier J. Sieiro
Integr.2
2014 Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors
abstract
In this paper, a new methodology for the automated generation of the optimal performance trade-offs of integrated inductors is presented. The methodology combines a multiobjective optimization algorithm with electromagnetic simulation to get highly accurate results. A set of sized inductors is obtained showing the best performance trade-offs for a given technology. Unlike reported approaches for inductor synthesis, performance trade-offs are generated offline, i.e., before any specific inductance or quality factor are required. The tight efficiency versus accuracy trade-off of existing approaches is, in this way, avoided and performance evaluation via electromagnetic simulation becomes affordable.
Reinier Gonzalez-Echevarria, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández 0001, Javier J. Sieiro, Neus Vidal, José María López-Villegas
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.5
2010 Low-power current-reused RF front-end based on optimized transformers topology
Ignacio Gil, Ignasi Cairó, Javier J. Sieiro, José María López-Villegas
Integr.3
2009 CMOS single-ended-to-differential low-noise amplifier
Tomás Carrasco Carrillo, José Gabriel Macias-Montero, Aitor Osorio Martí, Javier J. Sieiro, José María López-Villegas
Integr.4