This paper presents an inductively assisted switched-capacitor (L-SC) converter that employs a small inductor to enable continuous voltage conversion above and below the native n:m conversion ratio of a series-parallel SC converter. Unlike buck and flying-capacitor multilevel converters, the employed inductor in the demonstrated converter delivers only a fraction of the load current rather than its entire value, whereas the embedded SC supplies the remaining amount and lowers the voltage swing across the inductor as well as its current ripple. To maintain high efficiency across a wide output voltage range (i.e., 0.5-to-2.5V), a reconfigurable L-SC converter structure is proposed that enables altering the series-parallel SC conversion ratio between three distinct values, 2:1, 3:1, and 3:2, to facilitate five L-SC operating modes (i.e.,2:1,3:2). The five modes specifically allow the converter to avoid operation near the native SC ratios via small duty cycles, which otherwise lead to high discharging currents in the flying capacitors and their associated switches, and hence, low conversion efficiency. Simulation results in 0.18µm CMOS demonstrate that the proposed reconfigurable five-ratio series-parallel L-SC topology achieves a 98% peak efficiency while delivering power at a density of 2.55W/mm3 and a peak power density of 10.18W/mm3 with an efficiency of 96.3%.

This paper introduces a resonant ladder topology that can provide non-unit fraction, N:N-1, resonant voltage conversion ratios while eliminating the charge-sharing loss of all flying capacitors in a converter using a single inductor. Instead of connecting the inductor at the output side, which places the switches between the inductor and capacitors and exposes them to high voltage swings, as in prior non-unit fraction resonant converters, the inductor in the proposed topology is arranged in a series tank configuration. Additionally, the suggested converter requires a two-phase switching sequence instead of a multi-phase one to soft charge all existing flying capacitors. Furthermore, the topology does not change the converter’s resonant frequency among the consecutive switching phases. Importantly, the parent SC topology of the proposed resonant converter is the SC ladder topology that achieves the minimum switch V-A stress applicable to all dc-dc converters for a given conversion ratio. The power FETs in the bottom (N–1) half bridges of the proposed ladder converter are operated as diodes to allow efficient continuous output voltage regulation below the native N:N-1 resonant ratio using frequency or duty modulation. Furthermore, to maintain high efficiency across a wide output voltage range, a recursive reconfiguration structure is introduced that enables altering N and the conversion ratio, N:N-1, offering multiple resonant ratios using a single tank-connected inductor without disconnecting a single capacitor or altering the resonant frequency. Circuit simulation results of a 0.18µm design demonstrate the principal advantages of the proposed recursive resonant converter, where greater than 80% efficiency is achieved, with a 95.6% peak value, over an output range from 0.4 to 1.4V under a load current of 6A.

This paper evaluates the equivalent input impedance, Zin, that a parallel synchronized switch harvesting on inductor (P-SSHI) rectifier presents to the internal current, iP, of a piezoelectric transducer. Unlike prior impedance modeling work, the charge balance principle is used in this paper to break down Zinunder a P-SSHI circuit into three shunt components that are independent of each other and solely determined by the internal capacitance, CP, and resistance, RP, of a piezoelectric transducer, as well as the rectifier’s dc load resistance, RL, respectively. By isolating the part of Zinthat relies on CP, the proposed modeling can quantify the enhancement that a P-SSHI interface circuit provides to the equivalent impedance of CP, and hence, the improvement to the piezoelectric transducer output power. This approach facilitates performance comparison between a P-SSHI and other piezoelectric interface circuits in terms of the improvement an interface provides to the equivalent impedance of the transducer’s internal capacitance, CP, independent of the transducer’s internal current, iP, which typically varies with the amount of power extracted in transducers of high electromechanical coupling. Another advantage of breaking down Zininto three independent shunt components is that the optimal dc load resistance, ${R_L}^{\ast}$, that maximizes the output power of a P-SSHI interface circuit can be directly found from Zin. The developed models are verified using circuit simulations.

This article introduces a fourth-order$G_{m}$-C low-pass filter for ECG detection that achieves high linearity despite operating under a 0.5 V supply by 1) placing the differential pairs (DPs) of the employed$G_{m}$stages in a two-loop feedback structure, 2) employing body-driven rather than gate-driven$G_{m}$DPs, and 3) using current mirrors in place of cascoded transistors in a conventional$G_{m}$stage. Measurement results of a$0.18~\mu $m CMOS prototype show that the proposed filter, operating with a$V_{\text {DD}}$of 0.5 V, achieves an third-order harmonic distortion (HD3) below −40 dB for input amplitudes up to 340 mVpp. With an integrated noise of$154.7~\mu $Vrmsover a 240-Hz bandwidth, the filter exhibits a dynamic range (DR) of 53.6 dB, which is competitive with previously reported works.

This paper presents a single-inductor resonant switched-capacitor (ReSC) ladder converter for steep N:1 step-down voltage conversion that can employ the same thin-oxide transistors used to implement the end-load digital processing, and hence, can be fully integrated on the same application SoC. By operating the bottom stack of the ReSC switches as diodes, the ReSC converter output voltage can be regulated continuously below the native resonant ratio using frequency or duty modulation while maintaining high efficiency as the converter output voltage is decreased. Simulation results in 0.18μm CMOS demonstrate that the proposed 5:1 ReSC topology achieves a 96.6% peak efficiency while delivering power at a density of 0.16W/mm3and a peak power density of 1.02W/mm3with an efficiency of 85.2%. A 2.3× improvement in the peak power density and 2.8% improvement in the peak-efficiency are achieved compared to the state-of-the-art.

This paper introduces an inductor-less 8-path twoway power divider that is realized by sequentially activating N two-port 2:1 switched-capacitor dc-to-dc converters via N nonoverlapping clock phases. Specifically, each path in the proposed widely tunable power divider splits input power between the two output ports by connecting two capacitors in series across the input port in one phase, which stores half of the average input voltage across each capacitor, and in the next phase, each capacitor is connected separately to an output port. Simulation results of a 65nm CMOS design demonstrate an excellent input and output impedance matching capability, an insertion loss below 2.8 dB, and a power consumption below 54 mW over a tunable range of 0.2 to 1.4 GHz. The amplitude (phase) imbalance is less than 0.3 dB (3°) over the range. The simulation results of IIP2, IIP3, and OP1-dB are 48.1 dBm, 15.8dBm, and 0.78dBm, respectively, and the noise figure is 3.1 dB, at 1 GHz center frequency.

This paper presents a switched-photovoltaic (SPV) ladder dc-dc converter that can extract nearly the maximum power available from a string of series-connected photovoltaic (PV) cells under nonuniform illumination and in environments of widely varying temperatures. The converter consists of two strings of PV cells. Instead of switching costly passive elements (i.e., inductors or capacitors) to perform input-to-output voltage conversion, one PV string is switched up and down periodically with respect to the other fixed string. In this way, the intrinsic capacitance in the flying PV string is used to shuttle any mismatch charge, induced by nonuniform illumination across a solar panel, sequentially between each two series-connected cells in a string to the output. Additionally, the implicit switched-capacitor ladder converter, established by the PV cells internal capacitance, allows reconfiguring the converter output terminal location within the fixed ladder, and hence the employed voltage conversion ratio, without degrading harvesting efficiency. Simulation results of a proof-of-concept design using radiation-hardened GaN devices demonstrate the efficiency advantage of the proposed SPV ladder over prior solutions, where up to 43% and 63% improvements in the efficiency are realized.

In this paper, we propose to implement the switching regulator in an envelope-tracking (ET) hybrid supply modulator (HSM) using a binary switched-capacitor (SC) dc-to-dc converter instead of a switched-inductor (SL) dc-to-dc converter. The output impedance of a SL converter is inductive in nature, which prevents the delivery of the high-frequency content of the envelope in wide-bandwidth signals. On the other hand, the proposed SC supply modulator is not limited by an inductive impedance, and hence, inherently exhibits immediate response, which facilitates high-efficiency ET despite the increasing bandwidth of RF signals. Additionally, SC supply modulators require only switches and capacitor, which can be integrated on the same transmitter microchip using the high-Q capacitors available in typical CMOS processes. Conversely, existing supply modulators require multiple off-chip or in-package inductors to realize high efficiency, which increase form factor and cost. Circuit simulation results in 0.18µm demonstrate the efficiency advantage of the proposed SC HSM over an SL HSM, where up to 11.7% improvement in the average efficiency is realized while tracking a 100-MHz bandwidth OFDM signal.

To improve power density, a symmetric switched-capacitor (SC) ladder buck (SLB) is proposed in this brief that eliminates the fixed ladder in an SC ladder buck (SCLB) by tying the dc nodes in two 180$^{\circ}$-phase-shifted cells together. Unlike flying capacitor multilevel converters (FCMCs) that minimize the inductor current ripple, the ladder topology within an SCLB splits the inductor current optimally among the ladder switches, such that the overall equivalent output resistance is minimized. M-phase interleaving is proposed in this brief to allow SLB to regain this current splitting capability when operating via duty cycles larger than 0.5. Simulation results of a six-level four-phase design in 180-nm CMOS verify the performance advantages of the proposed topology.

This article presents the modeling and optimization of a sense-and-set (SaS) rectifier. The basic equations governing the operation of a SaS rectifier are derived analytically using Laplace-transform techniques. An expression for the harvesting efficiency of a SaS rectifier is developed by evaluating the conduction and gate-drive losses as well as the output power of the rectifier. The derived expressions are then employed to locate the optimal design point of a SaS interface circuit. The proposed modeling approach reduces the required run time by more than 2000 times as compared to SPICE simulation without sacrificing accuracy. The following design parameters are determined for maximum efficiency: optimal relative size between the rectifier switches, total conductance of the rectifier, and sensing frequency. The close match between the theoretical expressions and circuit simulation results validates the proposed analysis.

Closed-form expressions for the output dc voltage and load power of commonly used switched-capacitor (SC) piezoelectric interface circuits are derived. The proposed analysis approach computes the equivalent impedance introduced by an interface circuit to a piezoelectric transducer (PT). The input impedance of an interface is estimated by evaluating the equivalent linear time-invariant (LTI) network of the periodically switched ac side in the interface circuit. The advantage of the proposed model is that it quantifies the improvement that a given interface circuit provides to the transducer source impedance independent of its load-controlled internal current. In addition, the optimal load value that maximizes the output power of an interface circuit can be readily found from the interface equivalent input impedance. Unlike prior approaches, the proposed analysis takes the transducer’s internal resistance into account, which allows for determining the maximum achievable harvesting efficiency of an interface. Interestingly, it is found that the maximum power that a bias-flip rectifier can extract from a PT is limited to only 81% of the theoretical maximum power available under conjugate impedance matching. The developed analysis has been verified through circuit simulations.

This paper presents a multilevel passive mixer topology that allows N-path filters to operate at millimeter-wave frequencies from sinusoidal clocks without suffering from on-time overlapping between the adjacent phases. For differential N-phase passive mixing, the topology consists of N/2+1 series-connected out-of-phase switch pairs that operate from N/2 evenly-phase-shifted 50%-duty clock waveforms. Through the proposed topology, tunable differential LO buffers with LC loads can be used to resonate the gate capacitance of the filter switches and hence lower the mixer dominant gate-drive power loss without degrading the filter noise figure, linearity, or stopband attenuation. Simulation results using 0.18μ m CMOS demonstrate that the proposed multilevel topology provides 7 dB, 9 dB, and 2.4 dB improvements in the achievable selectivity, in-band IIP3, and noise figure, respectively, over conventional 4-path architectures at high frequencies.

This paper introduces a modeling framework to predict the efficiency scaling of switched-capacitor (SC) dc-dc converters under power density constraints. A reference power density metric is introduced under which SC converters are integrated directly on silicon using the available decoupling capacitance without increasing the chip footprint. An analytical model is then employed to predict the scaled SC converter efficiency, where it is found that the efficiency scales inversely with the product of the chip clock frequency and the MOSFET intrinsic delay. Through a derived numerical model of the SC power density, it is shown that a ~ 0.5 W/mm2SC density is sufficient to satisfy portable SoC power management needs with over 80% SC efficiency across the International Technology Roadmap for Semiconductors. This is at minimal area penalty by utilizing the nominally required 0.5 nF/mm2decoupling capacitance for supply integrity.

Analysis and optimization of switched-capacitor (SC) dc-dc converters with a series inductive filter are developed. The steady-state output impedance of such SC resonant converters is calculated for a 2:1 conversion ratio. In addition, the necessary conditions for proper application of the output inductive filter are derived. The proposed optimization methodology applies numerical optimization to evaluate different loss components in order to find the optimal design point of highest conversion efficiency. This optimization method is verified through SPICE simulations on a 2:1 SC power stage in 65-nm CMOS process.

A novel double-bound hysteretic control of multi-phase switched-capacitor (SC) converters is presented. The technique adjusts the number of interleaved phases with the output load to significantly reduce the operating frequency of the control comparator, enabling the practical application of hysteretic control with large number of interleaved phases. Using the proposed technique, the maximum required speed of the hysteretic comparator is reduced from 7.3 Ghz to 1.8 Ghz in a 16-phase 2:1 SC converter, designed in 65-nm CMOS process. In addition, the achieved dynamic response with such control is much faster than any reported integrated converter. For a 1.2-V input voltage and 0.45-V output voltage, the regulator enables a 35-mVppoutput droop for a 50% load step, without using a decoupling capacitor. In addition, the output for a 100-mV input reference step settles in 2.8-ns. The SC converter's efficiency is not affected by such reconfigurable interleaving scheme and reaches 81%.

A novel ripple mitigation technique is proposed for switched-capacitor voltage regulators (SCVR), which eliminates the output voltage ripple without using multi-phase interleaving. An inner control loop matches the SCVR's switch current to the load current on a cycle by cycle basis. A 2-phase 3:2 SCVR is designed in 45-nm CMOS process with the proposed control. For a 1.8 V to 1.05 V /40 mA converter, the proposed mitigation loop reduces the peak-to-peak output ripple from 330 mVp-pto 17 mVp-p, using total output capacitance of 4 nF/A. In addition, the proposed technique yields excellent regulation transient response.