Performance spaces contain information about all combinations of attainable performance parameters of analog integrated circuits. Their exploration allows designers to evaluate given circuits without considering implementation details, making them a valuable tool to support the design process. The computation of performance spaces-even for a small number of considered parameters-is time-consuming because it requires solving multi-objective, non-convex optimization problems that involve costly circuit simulations. We present a numerical method for efficiently approximating high-dimensional performance spaces, which is based on the box-coverage method known from Pareto optimization. The resulting implementation not only outperforms state-of-the-art solvers based on the well-known Normal-Boundary Intersection method in terms of computational complexity, but also offers several advantages, such as a practical stopping criterion and the possibility of warm starting. Furthermore, we present an interactive visualization technique to explore performance spaces of any dimension, which can help system designers to make reliable topology decisions even without detailed technical knowledge of the underlying circuits. Numerical experiments that confirm the efficiency of our approach are performed by computing seven-dimensional performance spaces for an analog low-dropout regulator as used in the radio-frequency identification domain.

This paper presents an adaptation of the well-known normal boundary intersection (NBI) method for approximating complete feasible performance spaces of analog integrated circuits. Those spaces provide accurate information about all feasible combinations of competing performance parameters in a circuit. While the NBI-method is originally designed for computing the so-called Pareto front of a multi-objective optimization problem only, it can be adapted for approximating the complete performance space with some modifications. A scalarization into single-objective optimization problems is performed within our developed tool, which can be connected to any Spice-based simulator. Besides presenting the algorithm and its adaptations, the focus lies on investigating parallelization techniques and their effect on decreasing the computational time. Numerical experiments show the computed approximations of two- and three-dimensional performance spaces of several OTAs and compare the efficiencies of different parallelization schemes.