This paper proposes implementation-friendly and dynamically reconfigurable VLSI-algorithm for convolutional neural network (CNN) inference engine. Based on this algorithm and additionally suggested techniques, high-throughput and hardware-efficient architecture of kernel processing unit (KPU) for the CNN inference engine has been presented here. It specially enables the proposed CNN inference-engine to achieve efficient local data reuse for all the computations of state-of-the-art CNN models. Hardware implementation of such KPU on Zynq UltraScale+ ZCU102 FPGA-board is capable of delivering 3.68$\times$higher throughput and 3.40$\times$higher energy-efficiency than the contemporary designs in the literature. Furthermore, this work suggests hardware-efficient architecture of classify unit for the CNN inference engine. It delivers 79.44% better hardware efficiency than the state-of-the-art work, when implemented on FPGA platform. In addition, aforementioned efficient-architectures of KPU and classify unit are aggregated to construct energy-efficient and high-throughput design of a complete CNN inference-engine. It has been FPGA implemented, and ASIC synthesized as well as post-layout simulated in 28 nm FD-SOI technology node. Hence, the suggested CNN inference engine with 864 processing elements delivers a peak throughput of 6.65 TOPs while operating at a maximum clock frequency of 3.85 GHz. To the best of authors’ knowledge, such unified design and implementation of CNN inference engine (including both KPU and classify unit), which is specifically capable of supporting efficient reuse of local data for all computation while processing the state-of-the-art CNN models, has been reported for the first time in this paper. Finally, the proposed CNN inference engine has been functionally validated in the real-world test scenario for the object classification application, using contemporary CNN models.

The Pietra-Ricci index detector (PRIDe) has been recently proposed as one of the simplest techniques for centralized, data-fusion cooperative spectrum sensing, attaining robustness against time-varying signal and noise levels, constant false alarm rate, and high detection power. In this paper, we propose the design and implementation of the PRIDe detector, targeting field programmable gate array (FPGA) and application-specific integrated circuit (ASIC) solutions. Novel approaches are proposed for computing the PRIDe’s test statistic, including the absolute value of complex quantities, the complex multiplier-accumulator, and the spectrum occupancy decision. The absolute value operation, which is critical to the PRIDe test statistic computational cost, applies the coordinate rotation digital computer (CORDIC) algorithm as a low latency and resource-efficient option. Register transfer level (RTL) and Monte Carlo simulations show that the resulting ultra-low latency PRIDe detector architectures attain no performance loss with respect to floating-point simulations. One of the two proposed ASIC design versions of the PRIDe sensor occupies 34.9% lower area compared to the most area-efficient sensor reported in literature, whereas the other one is$5.7\times$faster than the fastest state-of-the-art sensor. In a nutshell, the proposed detector architecture delivers the highest area and power efficiencies, considering the scaled values of area-time product (ATP) and power-delay product (PDP) metrics, in comparison to implementations reported to date.

This paper proposes implementation-friendly cooperative spectrum-sensing (CSS) algorithm for the data fusion based cooperative cognitive-radio network. It has been designed with the notion of alleviating the computational complexity that results in efficient hardware design, without degrading the detection performance. In addition, this work presents hardware-efficient architecture of cooperative spectrum sensor (CSR), based on the suggested CSS algorithm and with the aid of resource-sharing architectural optimization. Extensive performance analysis of our CSS algorithm showed that the detection probability of 0.9 has been achieved at the signal-to-noise ratio (SNR) of −2.6 dB which is adequate for many real-world applications. Furthermore, hardware implementation of the proposed CSR architecture is carried out on the FPGA platform (Nexys-4 DDR Artix-VII board) and its functional validation is performed in real-world scenario. Subsequently, the suggested CSR is ASIC synthesized and post-layout simulated in UMC 90 nm-CMOS technology node. As a result, it occupies a silicon area of 0.0369 mm2 and it is capable of operating at a maximum operating frequency of 251 MHz. This design has a latency of 79 clock cycles and it delivers a sensing time of$0.31 ~\mu \text{s}$while operating at the aforementioned maximum clock-frequency. In comparison to the state-of-the-art implementation, the proposed CSR occupies 34.1% lesser area, delivers$10\times $shorter sensing time, and has achieved$15.45\times $better hardware efficiency.

This manuscript proposes hardware-efficient and high-throughput reconfigurable architecture of the channel decoder for unified decoding of LDPC or polar code. It has been designed based on the new dataflow technique for reconfigurable decoding that incurs lesser hardware resources in the decoder design. In addition, this work presents memory-organized architecture that exploits the shared-memory hardware and also excludes various conventional sub modules. Furthermore, this reconfigurable LDPC/polar decoder has been ASIC fabricated in UMC 110 nm-CMOS technology node, occupying an area of 1.96 mm2. It supports multiple code-rates and code-lengths that are compliant to mMTC and URLLC applications of 5G-NR wireless communication standard. At the supply voltage of 1.2 V, the proposed decoder-chip operates at the measured clock frequency of 72.7 MHz and delivers a data throughput of 3.35 Gbps that is$4{\times }$higher than the state-of-the-art implementation. It also consumes 15.8% lesser area and achieves$2.5{\times }$better hardware-efficiency in comparison to the contemporary works.

This work proposes implementation friendly algorithm for multicoset sampling based wideband spectrum sensing that alleviates computational space and enables parallel execution, incurring lower latency. Based on this proposed algorithm, we provide a new hardware-efficient VLSI architecture of wideband spectrum sensor (WSSR), which offers short sensing time while sensing the wideband spectrum. Additionally, this paper presents a comprehensive discussion of all the submodule micro-architectures of the proposed WSSR. Subsequently, extensive performance analyses performed in the AWGN channel environment have demonstrated that our WSSR delivers adequate detection probability of 0.9 at -5 dB of SNR. Furthermore, the proposed WSSR design also uses a Zynq UltraScale+ FPGA board with a$14.16~\mu \text{s}$sensing time and a 2.63 GHz maximum sensing bandwidth. Comparison of our hardware implementation results has shown that the proposed WSSR achieves 38.5% higher sensing bandwidth and 90% shorter sensing time, in comparison to the state-of-the-art work. Eventually, this paper concludes by showing the ASIC synthesis and post-layout simulation results of the proposed WSSR in 90 nm-CMOS technology, which senses$5.4\times $wider bandwidth than the state-of-the-art implementation.

This article proposes implementation-friendly Gerschgorin radii and center ratio (GRCR)-based cooperative spectrum sensing (CSS) algorithm with reduced computational complexity that delivers adequate performance in uniform- and nonuniform-dynamical noise-and-received signal power scenarios. Subsequently, a new VLSI architecture of cooperative spectrum sensor (CSR) based on the proposed GRCR algorithm and additional architectural optimization has been suggested that consumes lower area and delivers shorter sensing time. Performance analysis of our implementation-friendly GRCR-based CSS algorithm has been carried out under the Rayleigh fading channel, and it delivers adequate area under the receiver-operating-characteristic (ROC) curve (AUC) = 0.9 at an average signal-to-noise ratio (SNRavg) of −5 dB. Consecutively, an application-specific integrated circuit (ASIC) chip of the proposed CSR has been fabricated in the UMC 130-nm CMOS process. It occupies 0.27 mm2of the core area, and its maximum operating frequency is 88.8 MHz at 1.2 V of the supply voltage. At this clock frequency, our CSR delivers a sensing time of$5~\mu \text{s}$while processing the received signal samples from four secondary users in a cognitive-radio network. These ASIC-implementation results are compared with the reported works in the literature where our design has shown$45\times $and$12\times $better hardware efficiency and sensing time, respectively, compared to the state-of-the-art implementations.

This article proposes an uninterrupted processing technique for the convolutional neural network (CNN) accelerator. It primarily allows the CNN accelerator to simultaneously perform both processing element (PE) operation and data fetching that reduces its latency and enhances the achievable throughput. Corresponding to the suggested technique, this work also presents a low latency VLSI-architecture of the CNN accelerator using the new random access line-buffer (RALB)-based design of PE array. Subsequently, the proposed CNN-accelerator architecture has been further optimized by reusing the local data in PE array, incurring better energy conservation. Our CNN accelerator has been hardware implemented on Zynq-UltraScale + MPSoC-ZCU102 FPGA board, and it operates at a maximum clock frequency of 340 MHz, consuming 4.11 W of total power. In addition, the suggested CNN accelerator with 864 PEs delivers a peak throughput of 587.52 GOPs and an adequate energy efficiency of 142.95 GOPs/W. Comparison of aforementioned implementation results with the literature has shown that our CNN accelerator delivers 33.42% higher throughput and$6.24\times $better energy efficiency than the state-of-the-art work. Eventually, the field-programmable gate array (FPGA) prototype of the proposed CNN accelerator has been functionally validated using the real-world test setup for the detection of object from input image, using the GoogLeNet neural network.

This article proposes a low-latency parallel Jacobi-method-based algorithm for computing eigenvalues and eigenvectors of$n\times n$-sized real-symmetric matrix. It is a coordinate rotations digital-computer (CORDIC)-based iterative algorithm that comprises multiple rotations and hence the key contribution of our work is to reduce the time cost of each rotation. Thus, alleviating the total latency for computing eigenvalues and eigenvectors using the parallel Jacobi method. Based on this proposed algorithm and additional architectural optimizations, a new low-latency and highly accurate VLSI-architecture has been presented in this manuscript for computing eigenvalues and eigenvectors of real-symmetric matrix. Subsequently, this work proposes a reconfigurable algorithm and its VLSI-architecture for computing eigenvalues and eigenvectors of complex Hermitian (CH), complex skew-Hermitian (CSH), and real skew-symmetric (RSS) matrices. Performance analysis of the proposed architectures has demonstrated minimal error-percentage of 0.0106% which is adequate for the wide range of real-time applications. The proposed architectures are hardware implemented on Zynq Ultrascale+ field-programmable gate array (FPGA)-board that consumed short latency of$9.377~\mu \text{s}$while operating at maximum clock frequency of 172.75 MHz. Comparison of our implementation results with the reported works showed that the proposed architecture incurs 43.75% lower latency and 89.4% better accuracy than the state-of-the-art implementation.

Spectrum sensing is an imperative process that primarily affects the reliability of cognitive radio networks (CRNs). Cooperative spectrum sensing (CSS) is the contemporary process of detecting the occupancy of spectrum by licensed users in CRN. It outperforms the conventional stand-alone spectrum-sensing (SSS) algorithms. However, such CSS algorithms have higher implementation-complexity than SSS algorithms, resulting in higher resource utilization and alleviating the hardware efficiency. Our work focuses on the design of hardware efficient VLSI-architecture for such CSS algorithms. Specifically, this paper proposes reconfigurable VLSI-architecture of cooperative spectrum sensor (CSR) for both maximum-minimum eigenvalue (MME) and maximum eigenvalue (MED) based CSS algorithms for the data-fusion based CRN. This CSR architecture has been designed based on iterative and shift power-methods to compute maximum and minimum eigenvalues in MME and MED CSS-algorithms. The proposed reconfigurable-CSR is fabricated in UMC 130-nm CMOS process and it has a die dimension of h × w =3D 1.5 mm × 1.5 mm. Furthermore, this work presents the analysis of hardware-complexity, sensing-time and performance with the increasing number of secondary users (or antenna array of CSR) in CRN. Eventually, the fabricated ASIC chip of CSR has been tested and verified in a real-world test environment.

This article presents a hardware-friendly algorithm and architecture for cooperative spectrum sensing (CSS) in the data-fusion-based cognitive-radio (CR) network. The proposed VLSI-algorithm is based on the iterative power method and deflation technique that alleviate the computational complexity of conventional CSS algorithm with minimal performance degradation. In this work, a new hardware-efficient VLSI architecture of cooperative spectrum sensor (CSR) for the data-fusion center is presented, which supports up to six secondary users in the cooperative CR network. Its performance analysis under fading channel environment has been carried out where it delivers 0.8 detection probability ( Pd) at -8 dB of channel SNR with a false alarm rate of 0.1. It shows the minimum performance degradation of 0.057 dB at Pd= 0.88 compared to the conventional algorithm. The suggested CSR architecture has been application-specific integrated circuit (ASIC)-synthesized and postlayout simulated in UMC 90 nm-CMOS process. Thus, it occupies 2.4 mm2of the core area, consumes 36 mW of total power, and delivers a low sensing time of 60.41 μs while operating at a maximum clock frequency of 87.7 MHz. Comparison with the reported works indicates that the proposed design requires 40.3% lesser area, and it is 41% hardware efficient than the conventional implementation. Eventually, this design has been field-programmable gate array (FPGA) prototyped, and its functionality is verified in the real-world test environment.

This article proposes reconfigurable maximum a posteriori (MAP) decoding algorithm which operates in multiple radix modes to hard decode the information bits with variable throughput by consuming constant power. Subsequently, a new digital decoder-architecture for this MAP decoding algorithm has been designed that operates in radix-2/4/8 modes. Furthermore, reconfigurable microarchitectures of state-metric and logarithmic-likelihood-ratio (LLR) computation units are presented in this article. Performance analyses of the proposed algorithm have been performed in additive-white Gaussiannoise (AWGN) channel environment where it achieved a biterror-rate (BER) of 10-4at a signal-to-noise ratio (SNR) of 5 dB. Suggested multiple-radix MAP-decoder is fabricated in united-microelectronics-corporation (UMC) 130-nm-CMOS technology node and it occupies die and core areas of 2.35 and 1.28 mm2, respectively, operating at a maximum clock frequency of 204 MHz. This MAP decoder ASIC-chip delivers throughputs of 201, 403, and 605 Mb/s while operating in radix-2, 4 and 8 modes, respectively, consuming a total power of 92 mW. Our chip achieves 0.15 nJ/bit of energy efficiency, which is 30% better than the most energy-efficient implementation from literature. Likewise, it delivers 39% higher throughput and 70× better area-efficiency than the state-of-the-art work.

This paper proposes cyclostationary feature detection (CFD) based spectrum sensor for cognitive radio technology that consumes lower hardware resources and delivers shorter sensing time. We have addressed the challenge of efficiently implementing complex frequency-domain based CFD spectrum-sensing algorithm. Specifically, VLSI-architecture of 2048-point FFT module has been multi-level resource shared for the optimization. In addition, performance analyses results of our spectrum sensor are presented for 1024, 2048 and 4096 point FFT sizes where the proposed design delivered adequate detection-probability of 0.9 at -5 dB of SNR. This spectrum sensor is FPGA implemented and it showed that the hardware utilization has been improved due to 100% reduction in memory requirement and has archived a shorter sensing time of 0.4 ms which is 12.5× lesser compared to the state-of-the-art work.

In this paper, we present a new microarchitecture of low-density parity-check (LDPC) decoder compliant to the specifications of 5G new-radio (NR) wireless-communication standard. This work suggests a fully-parallel VLSI architecture for this decoder to achieve high throughput. The digital architecture of internal modules as well as system-level design of the LDPC decoder are presented here. The comprehensive bit-error-rate (BER) performance analyses of our LDPC decoder has been performed in additive-white Gaussian-noise (AWGN) channel environment for various number of decoding iterations and bit-quantization. It delivers a BER of 10-6at 1 dB of Eb/N0while decoding for 10 iterations with 7-bits quantization. In addition, FPGA implementation and post-route simulation of the proposed LDPC decoder are carried out that can decode an encoded LDPC code of 26112 code-length for 1/3 code-rate. Our decoder has achieved a throughput of 2.9 Gbps while operating at a clock frequency of 102 MHz. These implementation results are compared with the reported works where our design delivered 20× better throughput compared to the state-of-the-art LDPC decoders.

This brief presents new VLSI architecture of spectrum sensor based on maximum eigenvalue based detection (MED) algorithm for cognitive radio applications. Our contributions focus on the formulation of hardware friendly MED based spectrum sensing algorithm. In addition, we propose resource-shared VLSI architecture for this algorithm to further enhance the hardware efficiency and lower the sensing time. Performance comparison of MED and cyclostationary based spectrum sensing algorithms has been carried out in AWGN channel environment using OFDM modulation and demodulation where the MED based spectrum sensing algorithm delivered better performance than cyclostationary based spectrum sensing by 4.5 dB at the detection probability of 0.5. We have synthesized and post-layout simulated our spectrum sensor in UMC 90 nm-CMOS process. Thus, it occupies 0.42 mm2of core area and operates at maximum clock frequency of 406 MHz resulting in a sensing time of90%.

Hardware implementation of Floating Point Units (FPUs) has been a key area of research due to their massive area and energy footprints. Recently, a proposal was made to replace IEEE 754-2008 technical standard compliant FPUs with Posit Arithmetic Units (PAUs) due to the greater accuracy, speed, and simpler hardware design. In this paper, we present the architecture of a parameterized PAU generator that can generate PAU adders and PAU multipliers of any bit-width pre-synthesis. We synthesize generated arithmetic units using the parameterized PAU generator for 8-bit, 16-bit, and 32-bit adders and multipliers and compare them with IEEE 754-2008 compliant adders and multipliers. Both, synthesis for Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) are performed. In our comparison of m-bit PAU units with n-bit IEEE 754-2008 compliant units, it is observed that the area and energy of a PAU adder and multiplier are comparable to their IEEE 754-2008 compliant counterparts where m=n. We argue that an n-bit IEEE 754-2008 adder and multiplier can be safely replaced with an m-bit PAU adder and multiplier where m

We propose flexible-architecture for soft-input soft-output (SISO) decoder with radix-2/4/8 modes to support multiple data-rates. This work presents designs of major internal blocks of SISO decoder using extensive steering logic to support multiple radix operating-modes. These architectures enable efficient clock-gating of our decoder for low-power consumption in different operating modes. Subsequently, we have aggregated eight SISO decoders with quadratic-permutation-polynomial (QPP) interleavers/de-interleavers to design parallel-turbo decoder architecture which can operate in multi-radix mode. Suggested SISO decoder is ASIC synthesized and post-layout simulated in UMC 65 nm-CMOS process. Performance analyses in AWGN channel environment showed that the bit-error-rate (BER) of 10-4could be achieved at 5 dB and 0.8 dB for SISO and turbo decoders respectively. Implementation result shows that the suggested SISO decoder could achieve throughput in the range 270-810 Mbps with the corresponding power consumption range of 12.24-37.67 mW. In comparison to the state-of-the-art, our design achieved 38% higher throughput and 61% lower power consumption. Similarly, our multi-radix parallel-turbo decoder is hardware prototyped in 28 nm-CMOS Zynq-FPGA board. It delivers a range of data-rates from 80-320 Mbps operating at 160 MHz of clock frequency for 8 iterations.

In this study, coding performance of turbo decoder compliant to the physical layer of digital‐video‐broadcasting‐satellite‐services‐to‐handhelds (DVB‐SH) standard for additive‐white‐Gaussian‐noise (AWGN) and frequency selective fading channels are presented. The modulation of transmitted bits is carried out with orthogonal‐frequency‐division‐multiplexing (OFDM) technique, incorporating 1 K‐fast‐Fourier‐transform (1K‐FFI) where each subcarrier is modulated using quadrature‐phase‐shift‐keying (QPSG) or quadrature‐amplitude‐modulation (QAM) schemes. Performance analysis of turbo decoder for the decoding iterations of 3, 8, 14 and 18 as well as the sliding window sizes of 10, 20, 30 and 40 are investigated for both the channels. Discussion on the values of these design metrics to achieve optimum coding performance is also presented. The optimisation of system throughput for turbo decoder based on the decoding iteration and sliding window size for various processor speed ranging from 200 MHz to 1 GHz is carried out. Such an analysis is presented for non‐parallel radix‐2 as well as parallel radix‐4 configuration of turbo decoder to meet the system throughput specification of third‐generation wireless communication standard ranging from 100 to 300 Mbps. The coding performance of turbo decoder based on max‐log‐MAP, log‐MAP and Maclaurin series‐based algorithms are studied for both the channel conditions. Simultaneously, the running time for each of these algorithm in a 64 bit processor is also presented for comparison. Finally, the coding performance of turbo decoder for various code rates of 1/5, 2/9, 1/4, 2/7, 1/3, 2/5 and 1/2 are carried out.