We report our results on pulse-forming-line (PFL)-based CMOS pulse generator studies. Through simulations, we clarify the effects of PFL length, switch speed, and switch resistance on the output pulses. We model and analyze CMOS pulse generators with on-chip transmission lines (TLs) as PFLs and CMOS transistors as switches. In a 0.13- μm CMOS process with a 500- μm long PFL, post-layout simulations show that pulses of 10.4-ps width can be obtained. High-voltage and high-power outputs can be generated with other pulsed power circuits, such as Blumlein PFLs with stacked MOSFET switches. Thus, the PFL circuit significantly extends short and high-power pulse generation capabilities of CMOS technologies. A CMOS circuit with a 4-mm-long PFL is implemented in the commercial 0.13- μm technology. Pulses of ~116-ps duration and 205-300-mV amplitude on a 50-Ω load are obtained when the power supply is tuned from 1.2 to 1.6 V. Measurement connection setup is the main reason for the discrepancies among measurements, modeling, and simulation analyses.