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Abhilasha Aswal

dblp:117/2445 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2012
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 100%
Interdisciplinary, comprehensive, and emerging computing
1 paper
Computational finance and economics · 100%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › computer arithmetic
decimal floating-point arithmetic		 0.112012
On Basic Financial Decimal Operations on Binary Machines · IEEE Trans. Computers 2012
Processor architecture and microarchitecture
instruction set architecture		 0.112012
On Basic Financial Decimal Operations on Binary Machines · IEEE Trans. Computers 2012

Methods — techniques the papers use, named apart from their topics

error sequence analysis · 0.3decimal arithmetic emulation · 0.3
YearPublicationVenuePosition
2012 On Basic Financial Decimal Operations on Binary Machines
abstract
Financial transactions are specified in decimal arithmetic. Until the introduction of IEEE 754-2008, specialized software/hardware routines were used to perform these transactions but it incurred a penalty on performance. In this paper, we show that if binary arithmetic is used to emulate decimal operations, then arbitrary error sequences can be generated by carefully chosen sequences of transactions which can lead to monotonically increasing/decreasing capitalization errors. In addition, we describe methods for correctly performing basic decimal operations, such as addition, subtraction, multiplication, and division, on binary machines, which are not conformant with IEEE 754-2008 decimal floating point standard (ISO/IEC/IEEE 60559:2011), at high speed.
Abhilasha Aswal, Ganesh Perumal, G. N. Srinivasa Prasanna
 IEEE Trans. Computers1