Demo Data from VLDB 2026 / reviewers in the wild / expert
Nuno Diegues
dblp:117/3638 · also Nuno Lourenco Diegues
· DBLP profile ↗
12ranked-venue papers
11as first author
0since 2021 · last 2017
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 10 · 9 first-authorSoftware engineering, systems software and programming languages · 2 · 1 first-authorSecurity and privacy · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
5 papers |
Parallel and multicore computing · 67% Distributed systems · 20% Energy-efficient computing · 8% | |
| Databases, data mining, and information retrieval
1 paper |
Indexing and storage engines · 50% Distributed and cloud data management · 50% | |
| Software engineering, system software, and programming languages
2 papers |
Concurrent programming · 100% |
Topics — the 11 heaviest of 15, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing
transactional memory |
0.9 | 4 | 2017 | Seer: Probabilistic Scheduling for Hardware Transactional Memory · ACM Trans. Comput. Syst. 2017 ProteusTM: Abstraction Meets Performance in Transactional Memory · ASPLOS 2016 On the energy and performance of commodity hardware transactional memory · SIGMETRICS 2014 |
Parallel and multicore computing › transactional memory
hardware transactional memory |
0.3 | 1 | 2017 | Seer: Probabilistic Scheduling for Hardware Transactional Memory · ACM Trans. Comput. Syst. 2017 |
Distributed systems › transaction processing
transaction scheduling |
0.3 | 1 | 2017 | Seer: Probabilistic Scheduling for Hardware Transactional Memory · ACM Trans. Comput. Syst. 2017 |
Parallel and multicore computing
synchronization |
0.3 | 2 | 2017 | Time-warp: lightweight abort minimization in transactional memory · PPoPP 2014 Seer: Probabilistic Scheduling for Hardware Transactional Memory · ACM Trans. Comput. Syst. 2017 |
Concurrent programming
synchronization |
0.2 | 1 | 2016 | ProteusTM: Abstraction Meets Performance in Transactional Memory · ASPLOS 2016 |
Concurrent programming
transactional memory |
0.2 | 1 | 2016 | ProteusTM: Abstraction Meets Performance in Transactional Memory · ASPLOS 2016 |
Parallel and multicore computing
concurrent programming |
0.2 | 1 | 2014 | On the energy and performance of commodity hardware transactional memory · SIGMETRICS 2014 |
Processor architecture and microarchitecture
chip multiprocessor |
0.1 | 2 | 2017 | Seer: Probabilistic Scheduling for Hardware Transactional Memory · ACM Trans. Comput. Syst. 2017 On the energy and performance of commodity hardware transactional memory · SIGMETRICS 2014 |
Machine learning › Optimization for machine learning › model-based optimization
bayesian optimization |
0.1 | 1 | 2016 | ProteusTM: Abstraction Meets Performance in Transactional Memory · ASPLOS 2016 |
Distributed systems › distributed database
distributed transactions |
0.1 | 1 | 2016 | STI-BT: A Scalable Transactional Index · IEEE Trans. Parallel Distributed Syst. 2016 |
Distributed systems › consistency models
strong consistency |
0.1 | 1 | 2016 | STI-BT: A Scalable Transactional Index · IEEE Trans. Parallel Distributed Syst. 2016 |
Methods — techniques the papers use, named apart from their topics
online optimization · 0.8collaborative filtering · 0.8bayesian optimization · 0.8transactional indexing · 0.5distributed b+ tree · 0.5time-warp commit · 0.4multi-version concurrency control · 0.4probabilistic inference · 0.3dynamic locking · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2017 | Seer: Probabilistic Scheduling for Hardware Transactional MemoryabstractThe ubiquity of multicore processors has led programmers to write parallel and concurrent applications to take advantage of the underlying hardware and speed up their executions. In this context, Transactional Memory (TM) has emerged as a simple and effective synchronization paradigm, via the familiar abstraction of atomic transactions. After many years of intense research, major processor manufacturers (including Intel) have recently released mainstream processors with hardware support for TM (HTM). In this work, we study a relevant issue with great impact on the performance of HTM. Due to the optimistic and inherently limited nature of HTM, transactions may have to be aborted and restarted numerous times, without any progress guarantee. As a result, it is up to the software library that regulates the HTM usage to ensure progress and optimize performance. Transaction scheduling is probably one of the most well-studied and effective techniques to achieve these goals. However, these recent mainstream HTMs have some technical limitations that prevent the adoption of known scheduling techniques: unlike software implementations of TM used in the past, existing HTMs provide limited or no information on which memory regions or contending transactions caused the abort. To address this crucial issue for HTMs, we propose S eer , a software scheduler that addresses precisely this restriction of HTM by leveraging on an online probabilistic inference technique that identifies the most likely conflict relations and establishes a dynamic locking scheme to serialize transactions in a fine-grained manner. The key idea of our solution is to constrain the portions of parallelism that are affecting negatively the whole system. As a result, this not only prevents performance reduction but also in fact unveils further scalability and performance for HTM. Via an extensive evaluation study, we show that S eer improves the performance of the Intel’s HTM by up to 3.6×, and by 65% on average across all concurrency degrees and benchmarks on a large processor with 28 cores. Nuno Diegues, Paolo Romano 0002, Stoyan Garbatov |
ACM Trans. Comput. Syst. | 1 |
| 2016 | ProteusTM: Abstraction Meets Performance in Transactional MemoryabstractThe Transactional Memory (TM) paradigm promises to greatly simplify the development of concurrent applications. This led, over the years, to the creation of a plethora of TM implementations delivering wide ranges of performance across workloads. Yet, no universal implementation fits each and every workload. In fact, the best TM in a given workload can reveal to be disastrous for another one. This forces developers to face the complex task of tuning TM implementations, which significantly hampers their wide adoption. In this paper, we address the challenge of automatically identifying the best TM implementation for a given workload. Our proposed system, ProteusTM, hides behind the TM interface a large library of implementations. Underneath, it leverages a novel multi-dimensional online optimization scheme, combining two popular learning techniques: Collaborative Filtering and Bayesian Optimization. Diego Didona, Nuno Diegues, Anne-Marie Kermarrec, Rachid Guerraoui, Ricardo Neves, Paolo Romano 0002 |
ASPLOS | 2 |
| 2016 | STI-BT: A Scalable Transactional IndexabstractDistributed Key-Value (DKV) stores have been intensively used to manage online transaction processing on large data-sets. DKV stores provide simplistic primitives to access data based on the primary key of the stored objects. To help programmers to efficiently retrieve data, some DKV stores provide distributed indexes. Besides that, and also to simplify programming such applications, several proposals have provided strong consistency abstractions via distributed transactions. In this paper we present STI-BT, a highly scalable, transactional index for Distributed Key-Value stores. STI-BT is organized as a distributed B$^+$Tree and adopts an innovative design that allows to achieve high efficiency in large-scale, elastic DKV stores. As such, it provides both the desirable properties identified above, and does so in a far more efficient and scalable way than the few existing state of the art proposals that also enable programmers to have strongly consistent distributed transactional indexes. We have implemented STI-BT on top of an open-source DKV store and deployed it on a public cloud infrastructure. Our extensive study demonstrates scalability in a cluster of$100$machines, and speed ups with respect to state of the art up to$5.4\times$. Nuno Diegues, Paolo Romano 0002 |
IEEE Trans. Parallel Distributed Syst. | 1 |
| 2015 | Seer: Probabilistic Scheduling for Hardware Transactional MemoryabstractScheduling concurrent transactions to minimize contention is a well known technique in the Transactional Memory (TM) literature, which was largely investigated in the context of software TMs. However, the recent advent of Hardware Transactional Memory (HTM), and its inherently restricted nature, pose new technical challenges that prevent the adoption of existing schedulers: unlike software implementations of TM, existing HTMs provide no information on which data item or contending transaction caused abort. We propose Seer, a scheduler that addresses precisely this restriction of HTM by leveraging on an on-line probabilistic inference technique that identifies the most likely conflict relations, and establishes a dynamic locking scheme to serialize transactions in a fine-grained manner. Our evaluation shows that Seer improves the performance of the Intel TSX HTM by up to 2.5x, and by 62% on average, in TM benchmarks with 8 threads. These performance gains are not only a consequence of the reduced aborts, but also of the reduced activation of the HTM's pessimistic fall-back path. Nuno Diegues, Paolo Romano 0002, Stoyan Garbatov |
SPAA | 1 |
| 2015 | Bumper: Sheltering distributed transactions from conflicts
Nuno Diegues, Paolo Romano 0002 |
Future Gener. Comput. Syst. | 1 |
| 2015 | Self-tuning Intel Restricted Transactional Memory
Nuno Diegues, Paolo Romano 0002 |
Parallel Comput. | 1 |
| 2014 | Virtues and limitations of commodity hardware transactional memoryabstractOver the last years Transactional Memory (TM) gained growing popularity as a simpler, attractive alternative to classic lock-based synchronization schemes. Recently, the TM landscape has been profoundly changed by the integration of Hardware TM (HTM) in Intel commodity processors, raising a number of questions on the future of TM. Nuno Diegues, Paolo Romano 0002, Luís E. T. Rodrigues |
PACT | 1 |
| 2014 | STI-BT: A Scalable Transactional IndexabstractIn this article we present STI-BT, a highly scalable, transactional index for Distributed Key-Value (DKV) stores. STI-BT is organized as a distributed B+Tree and adopts an innovative design that allows to achieve high efficiency in large-scale, elastic DKV stores. We have implemented STI-BT on top of a mainstream open-source DKV store and deployed it on a public cloud infrastructure. Our extensive experimental study reveals the efficiency of our solution with demonstrable scalability in a cluster of 100 commodity machines, and speed ups with respect to state of the art solutions of up to 5.4x. Nuno Diegues, Paolo Romano 0002 |
ICDCS | 1 |
| 2014 | Time-warp: lightweight abort minimization in transactional memoryabstractThe notion of permissiveness in Transactional Memory (TM) translates to only aborting a transaction when it cannot be accepted in any history that guarantees correctness criterion. This property is neglected by most TMs, which, in order to maximize implementation's efficiency, resort to aborting transactions under overly conservative conditions. In this paper we seek to identify a sweet spot between permissiveness and efficiency by introducing the Time-Warp Multi-version algorithm (TWM). TWM is based on the key idea of allowing an update transaction that has performed stale reads (i.e., missed the writes of concurrently committed transactions) to be serialized by committing it in the past, which we call a time-warp commit. At its core, TWM uses a novel, lightweight validation mechanism with little computational overheads. TWM also guarantees that read-only transactions can never be aborted. Further, TWM guarantees Virtual World Consistency, a safety property that is deemed as particularly relevant in the context of TM. We demonstrate the practicality of this approach through an extensive experimental study, where we compare TWM with four other TMs, and show an average performance improvement of 65% in high concurrency scenarios. Nuno Diegues, Paolo Romano 0002 |
PPoPP | 1 |
| 2014 | On the energy and performance of commodity hardware transactional memoryabstractThe advent of multi-core architectures has brought concurrent programming to the forefront of software development. In this context, Transactional Memory (TM) has gained increasing popularity as a simpler, attractive alternative to traditional lock-based synchronization. The recent integration of Hardware TM (HTM) in the last generation of Intel commodity processors turned TM into a mainstream technology, raising a number of questions on its future and that of concurrent programming. Nuno Diegues, Paolo Romano 0002, Luís E. T. Rodrigues |
SIGMETRICS | 1 |
| 2013 | Bumper: Sheltering Transactions from ConflictsabstractThis paper addresses the issue of maximizing the efficiency and scalability of distributed transactional platforms, by introducing Bumper, a set of innovative techniques to minimize aborts of transactions in high-contention scenarios. At its core, Bumper relies on two key ideas: (1) sparing update transactions from spurious aborts when they access concurrently updated data, by attempting to serialize them in the past via a novel distributed concurrency control scheme that we call Distributed Time-Warping (DTW), and (2) avoiding aborts due to contention hot spots (that cannot be tackled by DTW) via a novel programming abstraction, called delayed actions, which allows to efficiently serialize, in an abort-free fashion, the execution of conflict-prone data manipulations. The techniques used in Bumper can be applied to a wide variety of transactional replication protocols to enhance their performance in contention intensive workloads. In this paper we show how they can be integrated with SCORe, a recent, highly-scalable genuine partial replication protocol. By means of an extensive evaluation using well-known benchmarks and a cluster of 160 nodes, we show that Bumper can boost performance up to 3x in conflict-intensive workloads, while imposing negligible (2.5%) overheads in uncontended scenarios. Nuno Diegues, Paolo Romano 0002 |
SRDS | 1 |
| 2013 | Practical Parallel Nesting for Software Transactional Memory
Nuno Diegues, João P. Cachopo |
DISC | 1 |