Data transmission in a binary partial-response channel is often accomplished using a concatenated code consisting of an inner modulation code and an outer error-correcting code (ECC). We consider two inner decoders for such a code, each consisting of a reduced-complexity sequence detector modified to provide an estimate of the reliability of each bit. These reliability values are then used by the outer decoder to achieve improved performance. Although one of these decoders is considerably simpler than the other, their performances were comparable in the cases we considered. Both achieve considerable improvement over a decoder that uses hard-decision decoding of the inner code.

Considers the concatenation of an inner matched-spectral-null (MSN) code with an outer error-correcting code to achieve improved performance on a partial-response channel in the presence of additive white Gaussian noise. The authors show how to modify the reduced-complexity Viterbi algorithm of Karabed and Siegel [1991] to produce reliability values for each bit using the procedure proposed by Hagenauer and Hoeher [1989]. These reliability values are then used by the outer decoder to achieve improved performance. The authors simulated a number of codes and observed improvements due to soft-decision decoding of 1-2 db.>

J.H. Conway and N.J.A. Sloane (1986) have introduced an algorithm for the exact maximum-likelihood decoding of the Golay (24, 12) code in the additive white Gaussian noise channel that requires significantly fewer computations than previous algorithms. An efficient bit-serial VLSI implementation of this algorithm is described. The design consists of two chips developed using path-programmable logic (PPL) and an associated system of automated design tools for three- mu m NMOS technology. It is estimated that this decoder will produce an information bit every 1.6-2.4 mu s. Higher speeds can be achieved by using a faster technology or by replicating the chips to perform more operations in parallel.>