In this paper, an effective method based on adaptive extended Kalman filter (AEKF) is proposed for detection of random FDIs against battery state-of-charge algorithms on cloud battery management platforms. First, the battery model is established and used with the AEKF to predict the battery response. Second, a residual signal (RS) is defined as the difference between the AEKF-based estimated battery voltage and the received voltage measurement. The FDIs are then detected based on a hybrid detection criterion mixing the Chi-squared test and Euclidean detector. The proposed mixed strategy improves the detection accuracy in terms of false negatives and false positives caused by noises and changes in battery operation. Regarding the latter point, the AEKF is equipped with a dedicated recursive least squares filter to accommodate real-time model changes. The proposed algorithm is developed and verified based on actual battery data related to high-capacity lithium-ion cells. The method is exposed to different case studies considering normal and attack conditions and a remarkable detection accuracy of about 98% is attained with no false positive in the presence of current and voltage noises up to ±10 mA and ± 3 mV.

Embedded systems are vulnerable to significant security threats from Fault Injection Attacks (FIAs), which allow attackers to gain access to confidential information. While various attack detectors have been proposed in the literature to detect different types of FIAs, these detectors themselves are susceptible to such attacks and can be compromised. Hence, the robustness of these detectors is critical in maintaining the security of embedded systems. The focus of this study is to evaluate the robustness of digital circuits and delay-based digital detectors against a new type of FIA called Power-Off Attack (POA). POA occurs when the power to the chip is turned off, and the detectors are not active. Following a POA attack, the circuit or its detectors may not function properly when the power is turned back on, which can allow other attacks to be applied without being detected if the detectors are less sensitive. This study implements two detectors on Xilinx Artix-7 FPGAs and examines the impact of heating cycles on detector characteristics when the FPGA is in various states, including power-off, power-on, and inactive states (such as clock-freezing mode). Our experiments reveal that heating cycles in power-off mode can alter the FPGA component delays and the accuracy of its detectors, which highlights the vulnerability of these systems to POA and potential issues for embedded system security.

In this article, an efficient method for finite-time secure dynamic state estimation in cyber–physical systems (CPSs) subjected to unknown inputs and cyber-attacks is proposed. The proposed approach is based on a set of local finite-time state estimators operating over the subsets of sensory nodes, which are designed to estimate the states of the CPS subjected to unknown inputs. When cyber-attacks compromise some sensory nodes, the estimation results of the local finite-time estimators which use the measurements of the attacked sensors can be corrupted. An efficient detection algorithm is thus proposed to identify the valid local estimators that are completely devoid of the attacked sensory nodes. The information of the valid local estimators is then used to achieve secure state estimation and localization of the launched cyber-attack. The necessary and sufficient conditions for the feasibility and finite-time convergence of the proposed estimation mechanism are analytically derived and proven. The effectiveness of the proposed method is demonstrated by testing it on a dc electric motor. Likewise, some online software-in-the-loop tests are conducted to demonstrate the real-time feasibility of the proposed algorithm.

Internet of Things (IoT) is experiencing significant growth in the safety-critical applications which have caused new security challenges. These devices are becoming targets for different types of physical attacks, which are exacerbated by their diversity and accessibility. Therefore, there is a strict necessity to support embedded software developers to identify and remediate the vulnerabilities and create resilient applications against such attacks. In this paper, we propose a hardware security vulnerability assessment based on fault injection of an embedded application. In our security assessment, we apply a fault injection attack by using our clock glitch generator on a critical medical IoT device. Furthermore, we analyze the potential risks of ignoring these attacks in this embedded application. The results will inform the embedded software developers of various security risks and the required steps to improve the security of similar MCU-based applications. Our hardware security assessment approach is easy to apply and can lead to secure embedded IoT applications against fault attacks.

Dynamic-state estimation plays a critical role in achieving real-time wide-area monitoring of power systems. On the other hand, false data injection (FDI) attacks are substantial threats, which can undesirably ruin the state estimation results. To tackle this problem, an effective secure hybrid dynamic-state estimation approach that involves a dynamic model of the attack vector is proposed in this article. In the proposed method, an initial estimation of the system states is first obtained using a designed unknown input observer (UIO). Subsequently, based on the system, UIO models, and the initial estimations of the states, a dynamic model for the attack vector is extracted. Ultimately, the attack model is augmented with the main system model for coestimation of the attack and the system states using a Kalman filter. The onset of the FDI attack is rapidly detected by the accurate estimation of the attack vector. The effectiveness of the proposed approach is demonstrated under different FDI attack scenarios by a thorough theoretical analysis as well as simulations on IEEE 14-bus and 57-bus test systems. In order to show that the proposed method can keep up with typical scan rates of commercial phasor measurement units, a series of software-in-the-loop experiments are also conducted and the real-time feasibility of the proposed approach is guaranteed.

IC design and manufacturing chains show steadily growing complexity which provides different third party roles in between. Reprobate parties can take the opportunity to steal a client's IP or insert their malicious circuits-Hardware Trojans-in the original client's design and trigger them in case of need. Trojans are usually inserted in the most hidden internal signals with the lowest activity which increase their chance for not being activated and revealed by clients or end-users. In this paper we propose a method to reduce the number of signals with low activity and hence the chance of inserting hidden trojans. This method is based on an enhanced Logic Encryption approach and uses a 128-bit key. Encryption can also secure the design against IP piracy. Simulation results show that the proposed method can eliminate 83.17% of low activity signals in the circuit.