Searching for a line on the plane with n unit speed robots is a classic online problem that dates back to the 50’s, and for which competitive ratio upper bounds are known for every n ≥ 1, see [Baeza-Yates and Schott, 1995]. In this work we improve the best lower bound known for n=2 robots [Baeza-Yates and Schott, 1995] from 1.5993 to 3. Moreover we prove that the competitive ratio is at least √{3} for n=3 robots, and at least 1/cos ({π/n}) for n ≥ 4 robots. Our lower bounds match the best upper bounds known for n ≥ 4, hence resolving these cases. To the best of our knowledge, these are the first lower bounds proven for the cases n ≥ 3 of this several decades old problem.

A digital low-dropout (DLDO) voltage regulator circuit is proposed utilizing a multi-phase VCO based time quantizer. This high-resolution quantizer requires much lower sampling clock frequency compared to the previously proposed 1-bit comparator based architectures and thereby ensures stability over a wide operating condition, while reducing the dynamic power consumption at the same time. The DLDO operates at an input voltage range of 0.6V to 1.2V and delivers a maximum 115mA current with a 50mV dropout, simulated in a 65nm LP CMOS technology. A dynamically adaptive sampling clock can reduce the output voltage droop by 40-60% and provides 3.5-6.5 times faster settling compared to a baseline DLDO design that uses a fixed sampling clock frequency. The FOM calculated at 0.9V output is 0.53ps. The maximum current efficiency is 99.3%.

The output driver of the HDMI transmitter is designed in 32nM using MOS of 28 Å gate oxide thickness. These MOS transistors are capable of handling 1.8v only. The circuit protects the MOS transistors exposed to 3.3v at the receiver termination, when the transmitter is power on, as well as, when it is power off. The area of the implemented HDMI Transmitter physical layer is 0.283mm2and power consumption is 12mW @ 2.22Gbps (740Mbps/Channel) as seen on silicon.