This paper presents an enhanced floating-point multiply-add (FMA) design for the Intel E-Core processor. FMA is one of the most widely used operation in many applications. The proposed FMA is executed in 4 cycles, fully pipelined, handles SSE/AVX operations for scalar/packed IEEE single and double precision, and supports all four rounding modes. Also, the proposed FMA fully supports both denormal inputs and underflow outputs without microcode assistance. To achieve the 4-cycle FMA with full denormal support, several optimization techniques are applied: one-way alignment, radix-16 Booth encoding for the multiplier, merged J-bit correction and aligned significand with the multiply array, modified leading zero anticipation (LZA) for masking the underflow, parallel sticky and all-ones detection with the normalization, and merged two’s complement with the rounding logic. As a result, the proposed FMA achieved not only full denormal support but also about 10 – 30% reduced area and about 10 – 20% reduced latency compared to the traditional FMAs.

This paper presents an enhanced floating-point adder (FADD) design for the Intel E-Core processor. Floating-point addition and subtraction are two of the most widely used operations in many applications. The proposed FADD is executed in 2 cycles, fully pipelined, handles SSE/AVX operations for scalar/packed IEEE single and double precision, and supports all four rounding modes. Also, the proposed FADD fully supports both denormal inputs and underflow outputs without microcode assistance. To achieve the 2-cycle FADD with full denormal support, several optimization techniques are applied: split path algorithm, early alignment and sticky logic, parallel addition, rounding and all-ones detection, and modified leading zero anticipation (LZA) for masking the underflow. As a result, the proposed FADD achieved not only full denormal support but also about 12.5% reduced latency compared to the traditional FADD designs.

This paper presents improved architectures for a floating-point fused two-term dot product unit. The floating-point fused dot product unit is useful for a wide variety of digital signal processing (DSP) applications including complex multiplication and fast Fourier transform (FFT) and discrete cosine transform (DCT) butterfly operations. In order to improve the performance, a new alignment scheme, early normalization, a four-input leading zero anticipation (LZA), a dual-path algorithm, and pipelining are applied. The proposed designs are implemented for single precision and synthesized with a 45nm standard cell library. The proposed dual-path design reduces the latency by 25% compared to the traditional floating-point fused dot product unit. Based on a data flow analysis, the proposed design can be split into three pipeline stages. Since the latencies of the three stages are fairly well balanced, the throughput is increased by a factor of 2.8 compared to the non-pipelined dual-path design.