Brain-Computer Interfaces (BCIs) have the potential to restore motion for patients suffering from spinal cord injuries. Making such systems embedded, or even implantable, imposes strict low power constraints. Feature extraction, which transforms brain signals into intermediate representations before decoding motor intent, is typically the most compute intensive step. In this work, we introduce ALIFE-BCI, an Adaptive Quality Feature Extractor (AQFE), based on a Continuous Wavelet Transform (CWT) that captures the signal dynamics in both the time and frequency domains. The system is optimized with a top-down approach: (i) At the algorithmic level, it implements a piecewise linear approximation of the CWT that allows real-time energy-accuracy trade-offs. (ii) At the architectural level, memory reuse and parallelism are used to balance area and compute performance. (iii) At the circuit level, low-power techniques are used in a 22 nm FDSOI technology physical implementation flow. Three variants, with different levels of parallelism, are explored to extract 960 features at a rate of 10 Hz for a BCI motor application. The optimal variant, with an area of only 0.061 mm2, achieves 0.27 μW/feature at maximum quality, and 0.13 μW/feature at minimum quality, resulting in 8× lower power than existing digital solutions. Combined, these characteristics make the system well-suited for ultra-low-power implantable BCI decoders.

Uncertainty estimation in Neural Networks (NNs) is vital in improving reliability and confidence in predictions, particularly in safety-critical applications. Bayesian Neural Networks (BayNNs) with Dropout as an approximation offer a systematic approach to quantifying uncertainty, but they inherently suffer from high hardware overhead in terms of power, memory, and computation. Thus, the applicability of BayNNs to edge devices with limited resources or to high-performance applications is challenging. Some of the inherent costs of BayNNs can be reduced by accelerating them in hardware on a Computation-In-Memory (CIM) architecture with spintronic memories and binarizing their parameters. However, numerous stochastic units are required to implement conventional Dropout-based BayNN. In this paper, we propose the Scale Dropout, a novel regularization technique for Binary Neural Networks (BNNs), and Monte Carlo-Scale Dropout (MC-Scale Dropout)-based BayNNs for efficient uncertainty estimation. Our approach requires only one stochastic unit for the entire model, irrespective of the model size, leading to a highly scalable Bayesian NN. Furthermore, we introduce a novel Spintronic memory-based CIM architecture for the proposed BayNN that achieves more than 100× energy savings compared to the state-of-the-art. We validated our method to show up to 1% improvement in predictive performance and superior uncertainty estimates compared to related works.

In clinical trials, brain signal decoders combined with spinal stimulation have shown to be a promising means to restore mobility to paraplegic and tetraplegic patients. To make this technology available for home use, the complex brain signal decoding must be performed using a low-power, portable battery operated system. This case study shows how the decoding algorithm for a Brain-Computer Interface (BCI) system was ported to an embedded platform, resulting in an over 25 x power reduction, compared to the previous implementation, while respecting real-time and accuracy constraints.

Multipillar spintronic memory has emerged as a promising candidate for next-generation magnetoresistive random access memory (MRAM), offering advantages such as low power consumption, high integration density, and suitability for in-memory computing and neuromorphic applications. However, the intricate fabrication of multipillar structures increases susceptibility to manufacturing defects, necessitating robust and efficient testing methodologies. In this work, we analyze a singlecell spin-orbit torque (SOT)-based multipillar MRAM device under various resistive bridges, open defects, and transistor stuck-on/stuck-open faults. Corresponding fault models such as stuck-at faults (SAFs), transition faults (TFs), coupling faults (CFs), and read disturbance faults (RDFs) are proposed. A dedicated test algorithm is developed to detect these faults using a multilevel sensing scheme. It offers full coverage of all SAFs, TFs, CFs, and RDFs, and enables concurrent testing of multiple MTJs to significantly reduce test time. The proposed approach provides a robust design for testing framework for emerging multilevel SOT-MRAM architectures.

Bayesian Neural Networks (BayNNs) naturally provide uncertainty in their predictions, making them a suitable choice in safety-critical applications. Additionally, their realization using memristor-based in-memory computing (IMC) architectures enables them for resource-constrained edge applications. In addition to predictive uncertainty, however, the ability to be inherently robust to noise in computation is also essential to ensure functional safety. In particular, memristor-based IMCs are susceptible to various sources of non-idealities such as manufacturing and runtime variations, drift, and failure, which can significantly reduce inference accuracy. In this paper, we propose a method to inherently enhance the robustness and inference accuracy of BayNNs deployed in IMC architectures. To achieve this, we introduce a novel normalization layer combined with stochastic affine transformations. Empirical results in various benchmark datasets show a graceful degradation in inference accuracy, with an improvement of up to 58.11%.

Internet of Things (IoT) and smart wearable devices for personalized healthcare will require storing and computing ever-increasing amounts of data. The key requirements for these devices are ultra-low-power, high-processing capabilities, autonomy at low cost, as well as reliability and accuracy to enable Green AI at the edge. Artificial Intelligence (AI) models, especially Bayesian Neural Networks (BayNNs) are resource-intensive and face challenges with traditional computing architectures due to the memory wall problem. Computing-in-Memory (CIM) with emerging resistive memories offers a solution by combining memory blocks and computing units for higher efficiency and lower power consumption. However, implementing BayNNs on CIM hardware, particularly with spintronic technologies, presents technical challenges due to variability and manufacturing defects. The NeuSPIN project aims to address these challenges through full-stack hardware and software co-design, developing novel algorithmic and circuit design approaches to enhance the performance, energy-efficiency and robustness of BayNNs on sprintronic-based CIM platforms.

Bayesian Neural Networks (BayNNs) can inherently estimate predictive uncertainty, facilitating informed decision-making. Dropout-based BayNNs are increasingly implemented in Spintronics-based computation-in-memory architectures for resource-constrained yet high-performance safety-critical applications. Although uncertainty estimation is important, the reliability of Dropout generation and BayNN computation is equally important for target applications but is overlooked in existing works. However, testing BayNNs is significantly more challenging compared to conventional NNs, due to their stochastic nature. In this paper, we present for the first time the model of the non-idealities of the Spintronics-based Dropout module and analyze their impact on uncertainty estimates and accuracy. Furthermore, we propose a testing framework based on repeatability ranking for Dropout-based BayNN with up to 100% fault coverage while using only 0.2% of training data as test vectors.

With the adoption of smart systems, artificial neural networks (ANNs) have become ubiquitous. Conventional ANN implementations have high energy consumption, limiting their use in embedded and mobile applications. Spiking neural networks (SNNs) mimic the dynamics of biological neural networks by distributing information over time through binary spikes. Neuromorphic hardware has emerged to leverage the characteristics of SNNs, such as asynchronous processing and high activation sparsity. Therefore, SNNs have recently gained interest in the machine learning community as a brain-inspired alternative to ANNs for low-power applications. However, the discrete representation of the information makes the training of SNNs by backpropagation-based techniques challenging. In this survey, we review training strategies for deep SNNs targeting deep learning applications such as image processing. We start with methods based on the conversion from an ANN to an SNN and compare these with backpropagation-based techniques. We propose a new taxonomy of spiking backpropagation algorithms into three categories, namely, spatial, spatiotemporal, and single-spike approaches. In addition, we analyze different strategies to improve accuracy, latency, and sparsity, such as regularization methods, training hybridization, and tuning of the parameters specific to the SNN neuron model. We highlight the impact of input encoding, network architecture, and training strategy on the accuracy-latency tradeoff. Finally, in light of the remaining challenges for accurate and efficient SNN solutions, we emphasize the importance of joint hardware-software codevelopment.

Typical neural networks are incapable of effectively estimating prediction uncertainty, leading to overconfident predictions. Estimating uncertainty is crucial for safety-critical tasks such as autonomous vehicle driving and medical diagnosis and treatment. Bayesian Neural Networks (BayNNs), which combine the capabilities of neural networks and Bayesian inference, are an effective approach for uncertainty estimation. However, BayNNs are computationally demanding and necessitate substantial memory resources. Computation-in-memory (CiM) architectures uti-lizing emerging resistive non-volatile memories such as Spin- Orbit Torque (SOT) have been proposed to increase the resource efficiency of traditional neural networks. However, training scalable and efficient BayNNs and implementing them in the CiM architecture presents its own challenges. In this paper, we propose a scalable Bayesian NN framework via Subset-Parameter inference and its Spintronic-based CiM implementation. Our method is evaluated on large datasets and topologies to show that it can achieve comparable accuracy while still being able to estimate uncertainty efficiently at up to 70 × lower power consumption and 158.7× lower storage memory requirements.

The shrinking of technology nodes has led to high density memories containing large amounts of transistors which are prone to defects and reliability issues. Their test is generally based on the use of well-known March algorithms targeting Functional Fault Models (FFMs). This paper presents a novel approach for memory testing which relies on Cell-Aware (CA) methodology to further improve the yield of System on Chips (SoCs). Consequently, using CA methodology converts memory testing from functional to structural testing. In this work, the preliminary flow of the CA-based memory testing methodology is presented. The generation of the CA model for the SRAM bit cell has been demonstrated as a case study. The generated CA model and the structural representation of the memory are used by the ATPG to test the bit cell in the presence of short and open defects. The generated test patterns are able to detect both static and dynamic faults in the bit cell with a test coverage of 100%.

Bio-inspired Spiking Neural Networks (SNNs) are promising candidates to replace standard Artificial Neural Networks (ANNs) for energy-efficient keyword spotting (KWS) systems. In this work, we compare the trade-off between accuracy and energy-efficiency of a gated recurrent SNN (Spik-GRU) with a standard Gated Recurrent Unit (GRU) on the Google Speech Command Dataset (GSCD) v2. We show that, by taking advantage of the sparse spiking activity of the SNN, both accuracy and energy-efficiency can be increased. Lever-aging data sparsity by using spiking inputs, such as those produced by spiking audio feature extractors or dynamic sensors, can further improve energy-efficiency. We demonstrate state-of-the-art results for SNNs on GSCD v2 with up to 95.9% accuracy. Moreover, SpikGRU can achieve similar accuracy than GRU while reducing the number of operations by up to 82%.

The implementation of Artificial Neural Networks (ANNs) using analog Non-Volatile Memories (NVMs) for synaptic weights storage promises improved energy-efficiency and higher density compared to fully-digital implementations. However, NVMs are prone to variability, resulting in a degradation of the accuracy of ANNs. In this paper, a general methodology to evaluate and enhance the accuracy of neural networks implemented with non-ideal multi-level NVMs is presented. A hardware fault model distinguishing two types of errors, namely static and dynamic, capturing the variability of NVMs is proposed. Considering various neural networks, it is shown that error-aware training highly increases the robustness to errors compared to a standard, error-agnostic, training. Moreover, Recurrent NNs (RNNs) and Spiking NNs (SNNs) are found to be inherently more robust to dynamic errors than Convolutional NNs (CNNs). In addition, new insights on the adaptability of neural networks to noisy multi-level NVMs are presented, which could further improve their robustness in this context. The methodology aims at providing tools for hardware-software co-design, paving the way for a broader use of multi-level NVM-based synapses.

In this paper we investigate the parameters that affect the minimum SRAM retention voltage$(\mathbf{V}_{\mathbf{RET}})$while considering the effects of aging, local and global process variation. We also examine how these factors vary at different realistic use case temperatures. It is a known fact that the minimum retention voltage to maintain data without corruption at the bit-cell level is higher at cold than at room temperature or even hot temperature. As the temperature increases, CMOS devices become leakier and IDDQ at the bit-cell level drastically increases. The review of the leakage current contributors is discussed in the case of 40nm technology nodes. Additionally, the effects of local and global process dispersion are discussed and illustrated with silicon measurement. As far as a very small amount of current is required to explain a bitflip, attention is paid to accurately simulate$\mathbf{V}_{\mathbf{RET}}$in the SPICE model. Simulation results demonstrate that the aging effect (NBTI) makes pull-up devices slower and this can affect$\mathbf{V}_{\mathbf{RET}}$at the bit-cell level. As reported by measurement,$\mathbf{V}_{\mathbf{RET}}$is increased during the aging process. At product level, the specification of minimum voltage considers the worst case of operative condition (aging, temperature, process corner), it leads to pessimism and non-optimal power efficiency that will be quantified. Issued from simulation, temperature distributions are explored to figure out the tradeoff between power efficiency and temperature dependence of$\mathbf{V}_{\mathbf{RET}}$.

New semiconductor technologies for advanced applications are more prone to defects and imperfections related, among several different causes, to the manufacturing process, aging, and cross-talks. These phenomena negatively affect the circuit’s timing and can be effectively modeled by means of the path delay fault (PDF) model. While path delay testing is currently supported by commercial automatic test pattern generation tools for scan designs, functional testing covering PDFs is not widely adopted, mainly because of the high cost for test generation. On the other side, functional test is already widely adopted for in-field test of stuck-at faults (SAFs), which is often performed resorting to the execution of suitable test programs (Self Test Libraries, or STLs). This approach is attractive, since it can be performed at-speed with limited time constraints and high flexibility, making it a suitable in-field test solutions. Previous work assessed the feasibility and validity of functional approaches based on test programs targeting PDFs. In this work, we present the first systematic method for the development of very high fault coverage test programs for PDFs, which largely outperform test programs written for other fault models. Moreover, the proposed method allows the identification of functionally untestable faults. The effectiveness of the proposed approach was proven on an open-source RISC-V processor core, where 100% coverage of the functionally testable longest paths was achieved, compared with an initial coverage of 0.52% achieved with test programs targeting SAFs. Results demonstrate that shorter paths are also effectively covered.

Several recent studies have proposed the utilization of emerging technology devices, such as ReRAM, spintronic, and phase change memory in hardware-implemented neural network designs. However, the current poor maturity of the manufacturing process of memristive devices limits the implementation of synapses to low precision weights and to smaller size crossbars, which could be an issue for complex, higher dimensions machine vector learning tasks (e.g., object recognition, classifications, etc). Face to these challenges, efficient hardware implementations use binarization for weights and activation functions in the attempt to reach better energy efficiency, reduce the utilization of memory and the execution time. Moreover, to compensate the immaturity of the emerging devices technology and achieve better convergence, accuracy, and speed for learning and inference process, the neural network has to be designed either with an increased degree of redundancy, or with error correction capabilities. To avoid the inherent hardware cost of the redundancy and counteract the aforementioned issues, we propose an approach combining the concept of Ensemble Neural Networks paradigm with analog in-memory hardware implementation with spin-orbit torque (SOT) spintronic devices. These devices are among the most power-efficient emerging technologies. The architectural performances, power, and accuracy are verified on several datasets, showing that these combined approaches allow not only a very good resilience to high bit error rates but also a great reduction in execution time and number of memory accesses with a further reduction of$\times 100$for the energy consumption thanks to the SOT spintronic-based device.

Recent development in neural networks (NNs) has led to their widespread use in critical and automated decision-making systems, where uncertainty estimation is essential for trustworthiness. Although conventional NNs can solve many problems accurately, they do not capture the uncertainty of the data or the model during optimization. In contrast, Bayesian neural networks (BNNs), which learn probabilistic distributions for their parameters, offer a sound theoretical framework for estimating uncertainty. However, traditional hardware implementations of BNNs are expensive in terms of computational and memory resources, as they (i) are realized with inefficient von Neumann architectures, (ii) use a significantly large number of random number generators (RNGs) to implement the distributions of BNNs, and (iii) have a substantially greater number of parameters than conventional NNs. Computing-in-memory (CiM) architectures with emerging resistive non-volatile memories (NVMs) are promising candidates for accelerating classical NNs. In particular, spintronic technology, which is distinguished by its low latency and high endurance, aligns very well with these requirements. In the specific context of Bayesian neural networks (BNNs), spintronics technologies are very valuable, thanks to their inherent potential to act as stochastic or as deterministic devices. Consequently, BNNs mapped on spintronic-based CiM architectures could be a highly efficient implementation strategy. However, the direct implementation on CiM hardware of the learned probabilistic distributions of BNN may not be feasible and can incur high overhead. In this work, we propose a new Bayesian neural network topology, named SpinBayes , that is able to perform efficient sampling during the Bayesian inference process. Moreover, a Bayesian approximation method, called in-memory approximation , is proposed that approximates the original probabilistic distributions of BNN with a distribution that can be efficiently mapped to spintronic-based CiM architectures. Compared to state-of-the-art methods, the memory overhead is reduced by 8× and the energy consumption by 80×. Our method has been evaluated on several classification and semantic segmentation tasks and can detect up to 100% of various types of out-of-distribution data, highlighting the robustness of our approach, without any performance sacrifice.

This paper presents a full hardware implementation of a magnetic tunnel junction based stochastic tunable bitstream generator. It provides highly accurate control of the switching probability, while showing important robustness to process and temperature variations. We propose a new architecture of sensing scheme based on the pre-charged sense amplifier approach that uses an asynchronous digital module to control the internal signals of the sense amplifier with the purpose of improving the reliability against the timing hazards and reducing the power consumption by detecting the end of the reading to stop the required static currents. The circuit also features a digital feedback loop that analyzes the output bitstream and adapt the current in such a way that the bitstream encodes precisely the required probability. This circuit features an important bit generation rate at a low energy cost. Based on an exhaustive characterization of the circuit, we provide a behavioral description in Verilog, with timing and power files to be integrated as a standard cell in the digital design flow for application level evaluation of the performance. Thus, we also provide a design and evaluation flow from device to digital level of abstraction.

Deep Neural Networks (DNNs) are increasingly used in safety critical autonomous systems. In this paper, we present MOZART, a DNN accelerator architecture which provides fault detection and fault tolerance. MOZART is a systolic architecture based on the Output Stationary (OS) variant, as it is the one that inherently limits fault propagation. In addition, MOZART achieves fault detection with on-line functional testing of the Processing Elements (PEs). Faulty PEs are swiftly taken off-line with minimal classification impact. The implementation of our approach on Squeezenet results in a loss of accuracy of less than 3% in the presence of a single faulty PE, compared to 15-33% without mitigation. The area overhead for the test logic does not exceed 8%. Dropout during training further improves fault tolerance, without a priori knowledge of the faults.

The disruptive potential of the IEEE 1687 standard does not come from a single innovation, but rather from its capacity of providing a unified framework where heterogeneous approaches can co-exist and interact. In this Special Session, we will present the complementary research activities performed in the TIMA laboratory covering different aspects of the standard (Mixed-Signal instrument testing, Embedded Aging Monitors and Test Access Securization), and their coordination thanks to the Manager-for SoC Test (MAST) software environment.

Path Delay fault test currently exploits DfT-based techniques, mainly relying on scan chains, widely supported by commercial tools. However, functional testing may be a desirable choice in this context because it allows to catch faults at-speed with no hardware overhead and it can be used both for end-of-manufacturing tests and for in-field test. The purpose of this article is to compare the results that can be achieved with both approaches. This work is based on an open-source RISC-V-based processor core as benchmark device. Gathered results show that there is no correlation between stuck-at and path delay fault coverage, and provide guidelines for developing more effective functional test.

In this paper we present a novel hidden-delay-fault sensor design and a preliminary analysis of its circuit integration and applicability. In our proposed method, the delay sensing is achieved by sampling data on both rising and falling clock edges and using a variable duty cycle to control the length of the path to be tested. The main advantage of our proposed method is that it works at nominal frequency, it can detect hidden-delay-faults on short paths and it is versatile in its applicability. It can be used (i) during testing to perform user-defined hidden-delay-fault test, (ii) for reliability degradation estimation due to process, environmental variations and ageing, and (iii) in security to detect the insertion of Trojan horses that alter the path delay.

Interconnected devices communicate efficiently and securely over untrusted networks via security protocols that employ various encryption algorithms, often as hardware modules. State-of-the-art hardware implementations typically focus on optimizing a single metric and are tedious to adapt to a wider set of design constraints. In this work, we develop an open-source, flexible and parameterizable hardware implementation of the Advanced Encryption Standard (AES). We present a feature-rich implementation in Chisel that is simple to employ to any architectures and to fine-tune to specific design requirements. Despite the larger design space, we use 50% fewer lines of code than existing Verilog versions, thus enabling a higher level of development productivity.

The research work presented in this paper deals with the fault analysis in hardware-implemented Spiking Neural Networks with special emphasis on circuits designed to perform unsupervised, on-line learning. The paper describes the benefits of such neuromorphic systems, the possibilities of their hardware integration, but more importantly, it underlines the main concerns related to their resilience face to different types of faults. An overview of pertinent fault models and a methodology for conducting fault injection campaigns is described and different scenarios of faulty behaviors occurring after/before the STDP learning are shown.

Increasing demands from Autonomous Driving and IoT markets are pushing the need for products with advanced CMOS nodes that guarantee a high level of performance and at the same time having to comply with industrial regulatory standards like ISO26262, AEC-Q100 etc. Implementation of NBTI & DiR Reliability models for 28nm FDSOI, developed in-house, are fundamental means to evaluate the reliability of digital IPs during the design phase. Process, Temperature, Voltage, Workload based Aging are mission profile parameters traditionally taken into account for design margin evaluations and critical path pruning. A precise critical path selection methodology is highly important considering the In-situ monitor Insertion and Critical Path Replica generation strategies to be applied to Runtime Reliability assessment with the vision to move towards dynamic wear out management solutions. This paper recommends the consideration of the silicon technology feature of back biasing as an important parameter while selecting Critical Paths for circuits fabricated with FDSOI process. Back biasing is an add-on feature of this technology with ABB (adaptive back biasing) techniques having been used to compensate for PVT variations or aimed at a gain in the overall digital circuit performance. This technique is now being increasingly applied to aging mitigation. The back-biasing gain for an aged digital IP is quantified while performing design stage Gate Level Analysis yielding interesting insights on its impact on the operational frequency determining critical path rankings.

The emergence of non-volatile random access memory technologies, such as resistive and spintronic RAMs are triggering intense interdisciplinary activity. These technologies have the potential of providing many benefits, such as energy efficiency, high integration density, CMOS-compatibility, re-configurability, non-volatility and open the path towards novel computational structures and approaches, for the traditional Von-Neumann architectures and beyond. These promising characteristics, coupled with the ever-increasing limitations faced by traditional CMOS-based storage and computational structures, have driven the research community towards completely revisiting the existing computing and storage paradigms, now focusing on providing hardware solutions for in-memory and neuromorphic computing. This has resulted in an intensified research activity in the device physics, striving to achieve circuit-worth devices, reliable compact models and novel architectures. The purpose of this paper is to provide a comprehensive overview of the device physics, issues related to its use in electronic circuits, methodologies for their compact modelling and simulations, and their integration in storage and computational structures.

This paper provides an overview of the challenges faced by hardware implemented Spiking Neural Networks, from device to circuit design, reliability and test. We present a comprehensive description of the state-of-the-art neuromorphic architectures inspired by brain computation, with special emphasis on Spiking Neural Networks (SNNs), together with emerging technologies that have enabled such systems, namely Phase Change and Metal Oxide Resistive Memories. Finally, we discuss the main challenges faced by hardware implementations of SNNs, their reliability and post-fabrication test issues.

Silicon measurements indicate a change in frequency limiting path rankings as per aging and also as a function of workload. This paper proposes a simulation flow that leads to the identification of workload specific aged critical paths. Gate-level models are a means to estimate aging of the critical paths by taking into consideration the stress experienced by corresponding standard cells for a given digital circuit workload during circuit operational lifetime. We thus estimate the workload based aging margins for a particular design using this simulation flow.

The performance and low power requirement are becoming more and more challenging to fulfill for consumer product. On the opposite, a low failure rate at SoC level must be guaranteed to the end-customer. In that context, the insertion of in-situ slack monitor is known to be promising and efficient solution to manage the wear-out and more generally to minimize all margins related to manufacturing variations and operating conditions. As far as in-situ slack monitors are located in functional path, the choice of endpoint register and the number of monitors are of prime importance. This paper deals with a methodology of path selection in a context of monitor insertion in digital block without pattern availability. Basically, the timing of data path arriving to an endpoint register is analyzed, and a weight is calculated as a figure of merit. This work accounts for stochastic dispersion, aging, global corner process, voltage and temperature variations. The important role played by the sub-critical path is illustrated with silicon measurement.

The power and reliability issues of today's memories limit the improvements attained by their implementation in scaled technology nodes. Several emergent memory technologies attempt to address the technical constraints of today's memories, amongst which, one of the most promising solutions is the Spin-Transfer-Torque Magnetic Random Access Memories (STT-MRAMs). One of the great advantages of the emerging memories is that they favor increasing system complexity and performance. New applications and computation paradigms, such as neuromorphic computing, unfeasible a few years back due to technological limitations, can take profit from this technology. Intensive research has been conducted recently related to magnetic device physics and its implementation as dedicated hardware for neuromorphic computing, however, little work has been conducted to evaluate the reliability of such circuits. In this paper we investigate the effect of meaningful MTJ reliability issues on the behavior of an MTJ-based Spiking Neural Network.

Beyond CMOS, new technologies are emerging to extend electronic systems with features unavailable to silicon-based devices. Emerging technologies provide new logic and interconnection structures for computation, storage and communication that may require new design paradigms, and therefore trigger the development of a new generation of design automation tools. In the last decade, several emerging technologies have been proposed and the time has come for studying new ad-hoc techniques and tools for logic synthesis, physical design and testing. The main goal of this project is developing a complete synthesis and optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. New models for diode, FET, and four-terminal switch based nanoarrays are developed. The proposed methodology implements both arithmetic and memory elements, necessitated by achieving a computer, by considering performance parameters such as area, delay, power dissipation, and reliability. With combination of arithmetic and memory elements a synchronous state machine (SSM), representation of a computer, is realized. The proposed methodology targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories. The results of this project will be a foundation of nano-crossbar based circuit design techniques and greatly contribute to the construction of emerging computers beyond CMOS. The topic of this project can be considered under the research area of "Emerging Computing Models" or "Computational Nanoelectronics", more specifically the design, modeling, and simulation of new nanoscale switches beyond CMOS.

As systems become more complex, the size of transistors decreases. This effect leads to an increased probability of transient faults as well as higher variability of the transistors. Verifying that circuits are robust against transient faults and variability is mandatory. While formal verification may be used to prove robustness, a model that includes extracted electrical parameters and the corresponding timing information is usually too complex in practice. The contribution of this paper consists in a hybrid algorithm that can decide robustness. The algorithm uses Boolean reasoning as well as simulation to decompose the problem into feasible SAT formulas and still achieves completeness. In our experiments, we compare the algorithm against our previous implementation and achieve an average speed up of 1500 on the ISCAS-85 benchmarks and fault tolerant modifications.

Reliability for advanced CMOS nodes is becoming very challenging. The trade-off between high performance and reliability requirement can no longer be addressed by rough extra-margin. It would results in an overdesign and strong penalty of performance and area. A fine-grain analysis of mission profile is the path toward accurate assessment of ageing. A wide review of methodologies and results are presented, they are applied to digital, analog and RF/mmW circuits. Important set of experimental results are shown and compared to simulation. This paper highlights the correlation between activity profiling or workload and degradation performance induced by ageing.

With CMOS technology scaling, it becomes more and more difficult to guarantee circuit functionality for all process, voltage, temperature (PVT) corners. Moreover, circuit wear-out degradation lead to additional temporal variations, resulting in an important increase of design margins when targeting specific reliable systems (automotive or health care embedded applications) [1]. Adding pessimistic timing margin to guarantee all operating points under worse case conditions is no more acceptable due to the huge impact on design costs, such as up to 10% increase of slack time, with an upward trend as technology moves further.

Asynchronous circuits exhibit considerable advantages over their synchronous counterparts, like lower dynamic power and inherent variation tolerance, which makes them increasingly interesting. Their fault-tolerance behavior, however, is not yet fully explored. In particular, temporal masking, as seen with synchronous circuits, seems to be completely non-existent in asynchronous logic. Instead, there seem to be other masking mechanisms in the control structure that establish an extra barrier for transient fault propagation. In this paper we will explore these masking mechanisms in a qualitative as well as quantitative manner. To this end we first analyze the behavior of a Muller C-element, one fundamental building block in asynchronous designs. In a next step we evaluate the behavior of a chain of these elements, forming a so-called Muller pipeline, the basic control structure of many asynchronous designs, under transient faults. To validate our theoretical findings we inject radiation induced single event transients (SETs) in an extensive simulation campaign. The results show that the SET susceptibility of the Muller pipeline is indeed state dependent. This knowledge can be leveraged to improve, e.g., the radiation hardness of asynchronous circuits by preferring the more robust states in their design wherever possible.

This paper presents a cost-efficient Built-In Self-Test (BIST) scheme for fault detection and diagnosis of a cluster in a mesh FPGA. In this scheme, test cost reduction is achieved by simultaneous testing of logic and intra-cluster interconnect resources without degradation of diagnostic resolution. We analyze the impact of cluster size variation on the testability of a given cluster. Efficiency of this scheme is calculated in terms of the number of test configurations and the corresponding fault coverage for different cluster sizes. Moreover, automated tools developed for BIST implementation are integrated into the standard design flow for bitstream generation. Experimental results show that 100% stuck-at fault coverage can be obtained for a cluster with a gate level diagnostic resolution.

A fault tolerant routing algorithm for 2D Mesh Networks-on-Chip is presented in this work. It combines an adaptive routing algorithm with neighbor fault-awareness and a new traffic-balancing metric. To be able to cope with runtime failures that result in message corruption, the routing algorithm is enhanced with packet retransmission and a new packet recovery scheme. Simulation results, under various case studies, with different permanent, transient and intermittent link faults, and under different failure rates demonstrate the scalability and efficiency of the proposed algorithm to tolerate multiple failures likely encountered in deep submicron technologies.

This session brings together specialists from the DfT, DfY and DfR domains that will address key problems together with their solutions for the 14 nm node and beyond, dealing with extremely complex chips affected by high defect levels, unpredictable and heterogeneous timing behavior, circuit degradation over time, including extreme situations related with the ultimate CMOS nodes, where all processor nodes, routers and links of single-chip massively parallel tera-device processors could comprise timing faults (such as delay faults or clock skews); a large percentage of these parts are affected by catastrophic failures; all parts experience significant performance degradations over time; and new catastrophic failures occur at low MTBF.

Due to their scalability and flexibility, Networks-on-Chip are among the most popular communication fabrics for 3D integrated systems. 3D NoCs consist of a mix of inter-die and intra-die links implemented in different technologies. Thus, in order to guarantee correct data transmission through the 3D NoC, link reliability must be ensured. Error resilience techniques have been developed to protect links at the expense of increased area and power consumption, and reduced performance. In this paper, error resilience schemes are implemented for NoC links in stacked 3D integrated systems. We analyze, with respect to area / power overheads and reliability, the impact of inter-die and intra-die link-level error resilience techniques on a 3D NoC router architecture. Our results show that inter-die link protection with correction-based schemes and interleaved single error correction (SEC) codes are more efficient than traditional protection on all links.

Three-dimensional (3D) integration by die-/wafer-level stacking becomes a reality, as Through-Silicon-Via technologies emerge. However, poor reliability and yield of TSV interconnects remain major challenges of this promising technology. In this paper, we propose an efficient Built-In Self-Repair (TSV-BISR) strategy for TSV faults due to manufacturing and aging defects. After interconnect tests, we replace faulty TSVs with fault-free spares using shift operations. Among the benefits of this solution is that the self-repair signals are determined on-chip without any external intervention. Moreover, we show that with TSV-BISR better reparability is achieved with fewer spares than in existing TSV repair techniques. We also show that for 3D chips with interconnect reparability targets above 98% we reduce the area needed for spares and repair logic by up to 40%.

In 3D integrated systems, Thru-Silicon-Vias (TSVs) enable higher performance and energy efficiency, by reducing the data travel distances. However, the TSV manufacturing and wear-out defect rates lead to poor interconnect reliability and yield. The high fault rates and TSV footprint make spare-based repair solutions inefficient. I-BIRAS combines self-repair and adaptive serialization to increase yield and circuit life at the cost of lower throughput. After the interconnect test, the diagnosis vector DV is used to perform the self-repair and adaptive serialization to increase yield and circuit life at the cost of lower throughput. After the interconnect test, the diagnosis vector DV is used to perform the self-repair and adaptive serialization. The design parameters are the number of data bits n, the number of spare TSVs r, and the minimum acceptable number mLIMIT of fault-free TSVs. If the number of fault-free TSVs is less than mLIMIT then the link assumed failed.

Soft errors have been emerged as an important reliability concern of modern ICs. In this work we have implemented an efficient error detection scheme in a low power DSP/MCU processor. Our scheme achieves high error detection efficiency at low hardware cost by means of an original combination of double-sampling and latch based-design into the so-called GRAAL architecture. The implementation of our design in 65nm and 45nm process nodes has confirmed the advantages of the GRAAL architecture: low area and power penalties and negligible performance degradation. Its high error detection efficiency was demonstrated by performing extensive simulations of single-event transients (SETs).

In modern SoCs embedded memories concentrate the majority of defects. In addition defect types are becoming more complex and diverse and may escape detection during fabrication test, leading to field failures due to the use of faulty components in final products. As a matter of fact memories have to be tested by test algorithms achieving very high fault coverage for a increasingly complex faults. Fixing the test algorithm during the design phase may not be compatible with this goal, as unexpected failures not covered by this algorithm may be occur during production. Also, having the possibility to select the memory test algorithm after fabrication is very important during the initial phase of a new process node (both process debug and production ramp-up). Programmable BIST approaches, allowing selecting after fabrication a large variety of memory tests, are therefore desirable, but may lead on unacceptable area cost. BIST approaches enabling test algorithm programmability and data background programmability at low area cost have been presented in the past. However, no proposals exist for programming the address sequence used by the test algorithm. In this paper we expend programmable BIST to include address programmability. This new feature is implemented at low cost by using the memory under test itself to store the desired address sequence and some compact circuitry that enables using this sequence for testing the memory.

Scaling down in very deep submicron (VDSM) technologies increases the delay, power consumption of on-chip interconnects, while the reliability and yield decrease. In high performance integrated circuits wires become the performance bottleneck and we are shifting towards communication centric design paradigms. Networks-on-chip and stacked 3D integration are two emerging technologies that alleviate the performance difficulties of on-chip interconnects in nano-scale designs. In this paper we present a design-time configurable error correction scheme integrated at link-level in the 3D Spidergon STNoC on-chip communication platform. The proposed scheme detects errors and selectively corrects them on the fly, depending on the critical nature of the transmitted information, making thus the correction software controllable. Moreover, the proposed scheme can correct multiple error patterns by using interleaved single error correction codes, providing an increased level of reliability. The performance of the link and its cost in silicon and vertical wires are evaluated for various configurations.

In this paper configurable fault tolerant links are proposed for inter-die communication in stacked 3D SoCs. For high TSV fault rates, links degrade their performance by serial data transmission and signal remapping on the defect free wires. The link degradation is limited to a predetermined value, above which the link is considered non-functional.

The high defect rates of the TSV manufacturing processes lead to poor yield. Interconnect repair and serialization techniques were proposed to improve yield. In these papers the control of the repair and serialization circuitry are determined off-chip and are stored in one-time-programmable memories. In this work we present an Interconnect Built-in Self-Repair and Adaptive-Serialization approach (I-BIRAS), where interconnect repair and data serialization/deserialization is performed without external intervention (reducing cost of external equipment) and can be executed at any time (after fabrication and all along system life), thus coping with both fabrication and system-life defects.

Three-dimensional (3D) Thru-Silicon-Via (TSV) integration is emerging as a key enabling technology for future high performance systems. The TSV manufacturing defect rates lead to significant interconnect yield loss. For intra-die and inter-die interconnects, techniques such as via widening, via spreading and spare via insertion have been successfully used to improve the yield. However, for high fault rates these solutions are less effective and lead to unacceptable overheads. In this paper, configurable serial fault tolerant links are proposed for inter-die communication in 3D integrated systems. For high TSV fault rates, serial data transmission and signal remapping on fault-free wires are jointly used to ensure correct data transmission. After the interconnect tests, if faulty wires are detected then the link serializes data transmission such that only fault free wires are used. In the proposed link, any subset of data bits can be mapped on any subset of functional wires. Selecting a threshold serialization rate above which the link fails, enables optimal link designs that target interconnect technologies with high fault rates. The impact of inter-die configurable serial fault tolerant links on the performance and area overheads of 3D mesh networks-on-chip (3D NoC) is analyzed. The results show that for an 80% interconnect fault rate the latency degradation up to 14% and area overheads go up to 30%.

In the context of the emerging 3D integration paradigm, chips are built as stacks of several (likely heterogeneous) 2D layers. The topology of their communication network is quite irregular, mainly due to the different topologies of the 2D layers and the partial vertical connection between these layers. In this paper, a reconfigurable inter-layer routing mechanism (RILM) for such topologies is proposed. We firstly present the mechanism of composing the routing algorithms in different layers, through the vertical links, in order to achieve a multi-layer routing algorithm. Reconfiguration of the routing can be done for multiple reasons: to achieve fault-tolerant capability, but also under dynamic changing of the communication requirements, or, simply, to avoid congestions. To obtain a complete routing reconfiguration for the entire stack of layers, we propose a reconfiguration algorithm of the inter-layer routes, as a complement to the 2D routing reconfiguration. Additionally, independently of the 2D routing algorithm properties, RILM tolerates multiple failures of vertical links, as long as the stack of layers is not partitioned.

SoC development requires interaction between a wide range of engineering disciplines. Each of which brings in optimisation factors that impacts other disciplines. Therefore, concurrent development and end-to-end planning between these disciplines are necessary. This session will show the overlap between design, packaging, silicon manufacturing, test and yield optimisation.

This article deals with a built-in self-test method using only a one-bit ADC and a one-bit DAC. It is theoretically possible to use a binary white noise and binary observations to estimate the impulse response and the output of a linear system, provided this system has good mixing properties. We show how this can be easily implemented on digital programmable targets. The FPGA-based identification of the impulse response of a bandpass filter is performed and the experimental results are presented.

In this paper we propose a set of different configurations of failure recovery schemes, developed for network-on-chip (NoC) based systems. These configurations exploit the fact that communication in NoCs tends to be partitioned and eventually localized. The failure recovery approach is based on checkpoint and rollback and is aimed towards fast recovery from system or application level failures. The proposed recovery configurations and partitions of the NoC enhance the performance/overhead of the recovery mechanism. We analyze the effectiveness of these solutions, depending on the traffic characteristics and the expected failure rate.

This paper proposes a method of improving the scalability of checkpoint recovery for network-on-chip based systems in terms of checkpointing latency and memory requirements. The improvement considers the broadcasts implied in the checkpointing protocol. It combines the reduction of the number of broadcasts in the checkpoint synchronization protocol with the use of a more efficient broadcast method at network level.

Fault-tolerant design of network-on-chip communication architectures requires the addressing of issues pertaining to different elements described at different levels of design abstraction - these may be specific to architecture, interconnection, communication and application issues. Assessing the effectiveness of a particular fault-tolerant implementation can be a challenging task for designers, constrained with tight system performance specifications and other requirements In this paper, we provide a top-down view of fault-tolerance methods for NoC infrastructures, and present a range of metrics used for estimating their quality. We illustrate the use of these metrics by simulating a few simple but realistic fault-tolerant scenarios.

This paper presents a methodology for analyzing the behavior of nanometer technologies regarding "multiple event transients" (MET) caused by nuclear reaction induced by atmospheric neutrons. For the first time, currents collected by several sensitive areas of an ASIC cell resulting from a nuclear reaction are addressed by simulation. Libraries of several thousand types of currents are obtained for neutron energy range between 1 and 200 MeV. Group of currents are simultaneously injected at SPICE level and their effects are monitored on the cell output. Following an amplitude criterion, output transient duration and associated occurrence probability are recorded. A 130 nm NAND gate from ATMEL Corporation is first used to illustrate the methodology and a comparison between single event transients and multiple event transients effects is presented Finally, results regarding five different combinational cells in the ATMEL 130 nm library are presented and discussed.

This paper presents a new transistor level design flow where it is possible to optimize the circuit with a wide number of logic functions and drive strengths. Different from the standard cell approach, our methodology is not limited to a previously characterized library of cells. The proposed design flow provides a virtual library with around 15,000 cells for logic synthesis and performs a transistor sizing optimization step to improve the timing of the circuit during layout generation. A transistor-level layout generator allows to explore these wide number of cells and drive strengths while optimizing the layout concerning connections and transistors. Circuits generated by our methodology were compared to the standard cell approach in which presented around 11 % of delay improvement and more than 30% of power savings.

This panel will bring together a set of experts working in a collaborative project to address at both experimental measurement and simulations all levels of the process leading to system failures induced by soft errors. Several aspects will be discussed, e.g. interaction between energetic particles and the matter, detailed analysis of transient pulse generation and propagation, dependence of the circuit topology and system architecture.

This paper presents a new Monte-Carlo methodology to investigate the transient effect occurrence in complementary metal oxide semiconductor (CMOS) logic circuits: TMC DASIE (transient Monte-Carlo detailed analysis of secondary ion effects). The production and effects of single-event transients inside CMOS combinational logic gates are examined. First results and perspectives are presented

This paper reports a case study about the automatic layout generation and transient fault injection analysis of a phase-locked loop (PLL). A script methodology was used to generate the layout based on transistor level specifications. After layout validation, experiences were performed in the PLL in order to evaluate the sensibility against transient fault. The circuit was generated using the STMicroelectronics HCMOS8D process (0.18/spl mu/m). Results report the PLL sensitive points allowing the study and development of techniques to protect this circuit against transient faults.

This paper reviews the main approaches used to evaluate the effect of single event transients and single event upsets in digital circuits described at different abstraction levels. The two fault models are first discussed with respect to the circuit description levels, then complementary dependability evaluation methods are summarized.

This special session includes a presentation on nuclear codes used to determine a data-base of secondary ion species and their energies produced by the neutron-silicon and neutron-oxygen interactions, a presentation on FIT estimation tools using the secondary ions data-base created by the former codes and a presentation on design techniques suitable for mitigating the effects of ionising particles on modern nanometric designs.

Soft error rates induced by cosmic radiation become unacceptable in future very deep sub-micron technologies. Many hardening techniques at different abstraction levels have been proposed to cope with increased soft error rates. Depending on the abstraction level some techniques need to modify the design at architecture, circuit and transistor level, others required the modification of the circuit layout or to use new defined cells within the circuit. In this paper an automatic layout generator is presented to complete the system design process being able to easily generate the hardened design layout, thus reducing the system design time. This work aims at presenting a case study of a complete soft error tolerant integrated circuit by using an automatic layout generator called Parrot Punch.

Memory built in self repair (BISR) is gaining importance since several years. New fault tolerance approaches are mandatory to cope with increasing defect levels affecting memories produced with current and upcoming nanometric CMOS process. This problem will be exacerbated with nanotechnologies, where defect densities are predicted to reach levels that are several orders of magnitude higher than in current CMOS technologies. This work presents an evaluation of the area cost and yield of BISR architectures addressing memories affected by high defect densities. Statistical fault injection simulations were conducted on several memories. The obtained results show that BISR architectures can be used for future high defect technologies, providing close to 100% memory yield, by means of reasonable hardware cost.

Memory built in self repair (BISR) is gaining importance since several years. Because defect densities are increasing with submicron scaling, more advanced solutions may be required for memories to be produced with the upcoming nanometric CMOS process generations. This problem will be exacerbated with nanotechnologies, where defect densities are predicted to reach levels that are several orders of magnitude higher than in current CMOS technologies. For such defect densities, traditional memory repair is not adequate. This work presents a diversified repair approach merging ECC codes and self-repair, for repairing memories affected by high defect densities. The approach was validated by means of statistical fault injection simulations considering defect densities as high as 3*10/sup -2/% (3% of cells are defective). The obtained results show that the approach provides close to 100% memory yield, by means of reasonable hardware cost, for technologies of very poor quality. Thus, the extreme defect densities that many authors predict for nanotechnologies do not represent a show-stopper, at least as concerning memories.

This paper presents memory built-in self-repair approaches allowing to achieve high yield for defect densities several orders of magnitude higher than in current technologies. Such repair schemes illustrate that we could build memories in nanoelectronic technologies that are subject to very high defect densities.

Obsolescence of electronic components is a big concern affecting most electronic equipments involved in safety critical applications (automotive, avionics, airframe, nuclear plants, military applications...). Indeed, such applications are active years longer than was originally anticipated. This paper addresses a methodology to validate emulated replacement solutions and propose solutions to be experienced on a Motorola 6800 processor to illustrate the proposed approach.

IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly sensitive to noise, which will result in unacceptable rates of soft-errors. Furthermore, defect behavior is becoming increasingly complex resulting in increasing number of timing faults that can escape detection by fabrication testing. Thus, fault tolerant techniques will become necessary even for commodity applications. This work considers the implementation and improvements of a new soft error and timing error detecting technique based on time redundancy. Arithmetic circuits were used as test vehicle to validate the approach. Simulations and performance evaluations of the proposed detection technique were made using time and logic simulators. The obtained results show that detection of such temporal faults can be achieved by means of meaningful hardware and performance cost.

IC technologies are approaching the ultimate limits of silicon in terms of device size, power supply levels and speed. By approaching these limits, circuits are becoming increasingly sensitive to noise as well as to small manufacturing defects that may result in spurious faults. Such faults are difficult to (or can not) be detected by manufacturing testing and will result in unacceptable rates of errors in the field. Self-checking design can be used to cope with this problem, but usually it addresses logic faults. This paper analyzes the behavior of self-checking circuits under various spurious faults likely to occur in very deep submicron technologies.

This paper describes results on Built-In Current Sensors (BICS) destined to overcome the limitations of I/sub DDQ/ testing in deep submicron circuits. The problems of performance penalty, test accuracy and test speed are addressed. A new sensor composed of a source-controlled comparator operating at low supply voltages and bias currents is used. Gradual sensor activation ensures reliable low noise operation. It is combined with large bypass MOS switches avoiding performance penalty, as well as a second bypass and compensation logic to increase test speed.