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Kyle Balston

dblp:12/11438 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2013
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 91% Processor architecture and microarchitecture · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › coverage analysis
code coverage
0.212013
Post-Silicon Code Coverage for Multiprocessor System-on-Chip Designs · IEEE Trans. Computers 2013
Electronic design automation
hardware verification and test
0.212013
Post-Silicon Code Coverage for Multiprocessor System-on-Chip Designs · IEEE Trans. Computers 2013
Electronic design automation › hardware verification and test › design validation
post-silicon validation
0.212013
Post-Silicon Code Coverage for Multiprocessor System-on-Chip Designs · IEEE Trans. Computers 2013
Processor architecture and microarchitecture
chip multiprocessor
0.012013
Post-Silicon Code Coverage for Multiprocessor System-on-Chip Designs · IEEE Trans. Computers 2013

Methods — techniques the papers use, named apart from their topics

on-chip coverage monitors · 0.2
YearPublicationVenuePosition
2013 Post-Silicon Code Coverage for Multiprocessor System-on-Chip Designs
abstract
Effective techniques for post-silicon validation are required to better evaluate functional correctness of increasingly complex multi and many-core SoCs. However, there is little data evaluating the coverage of post-silicon validation efforts on industrial-scale designs. In this paper, we address this knowledge gap by instrumenting a nontrivial SoC with on-chip coverage monitors to measure the coverage achieved by typical post-silicon validation tests, such as booting the operating system (OS). We compare coverage achieved pre and post-silicon, and also measure the area overhead required to monitor post-silicon coverage. Our results show that the typical test of booting the OS often achieves high coverage, well correlated to what is achieved by pre-silicon directed tests, but in some blocks the coverage can be low or markedly different between pre and post-silicon, highlighting the importance of post-silicon validation in general and post-silicon coverage measurement in particular.
Kyle Balston, Mehdi Karimibiuki, Alan J. Hu, André Ivanov, Steve Wilton
IEEE Trans. Computers1