At CRYPTO 2019, Gohr applied deep learning to differential cryptanalysis of SPECK32/64, achieving identification accuracy surpassing that of traditional differential distinguishers. This achievement offers new perspectives for data security and privacy protection in the Internet of Things (IoT). However, existing research still faces challenges such as limited model accuracy and excessive computational resource consumption. To address these issues, we propose a novel enhanced model of differential neural distinguishers that balances high accuracy with low computational overhead. Initially, an innovative data feature extraction strategy is designed by introducing the skip connection mechanism to effectively integrate both linear and non-linear features extracted from the raw data. This allows the model to better approximate the internal mechanisms of cryptographic algorithms. Subsequently, based on the positional relationships of non-linear components within round functions and the diffusion properties of linear components, an original input data format selection strategy is proposed. We employ the multi-pair data augmentation strategy, significantly improving the model’s identification accuracy and generalization capabilities. Additionally, we pioneer the integration of an Efficient Channel Attention (ECA) module, to curtail the number of residual blocks required, thereby effectively reducing computational load. Furthermore, leveraging the algebraic expressions of cryptographic ciphers and the propagation characteristics of differential features, we develop a fast neutral bit search algorithm that enhances the efficiency of the key recovery process. Taking SIMON32/64 as an example, we successfully demonstrate a key recovery attack for 16 rounds with an accuracy rate of 80%.

Lightweight block ciphers are proposed for Internet of Things (IoT) edge devices to ensure secure data transmission with limited resources. However, past research has been designed on ideal channel models, disregarding the possibility of ciphertext errors caused by channel interference during actual transmission. This omission poses difficulties in ensuring the reliability of the ciphertext, especially in the Internet of Medical Things (IoMT) where resources are limited and data accuracy requirements are high. Designing a highly secure and reliable lightweight block cipher for such situations is one of the most challenging tasks. Hence, we propose a lightweight block cipher ECLBC with error detection and correction mechanisms. For security, ECLBC not only achieves a certain security level in fewer rounds but also achieves a mode transition within AND-Rotation-XOR (AND-RX) lightweight block ciphers. This transition involves a shift from the Feistel to the Substitution-Permutation Network (SPN) and from half-round key XOR to full-round key XOR. For reliability, ECLBC supports detecting and correcting erroneous ciphertext due to channel interference. Given the resource-constrained nature of IoMT devices, we implement the detection and correction mechanism of ECLBC based on the linear block code. Finally, various classical cryptography methods are employed to analyze the performance and security of the ECLBC.

The advancement of the Internet of Things (IoT) has promoted the rapid development of low-power and multifunctional sensors. However, it is seriously significant to ensure the security of data transmission of these nodes. Meanwhile, sensor nodes have the characteristics of converting analog signals into digital signals for operation processing in wireless sensor networks (WSNs). Given the particularity of Addition or AND, Rotation, and XOR (ARX) operations, its round function can only be based on the Feistel structure or generalized Feistel structure, otherwise, the process of decryption cannot be completed correctly. Furthermore, the existing ARX ciphers have the problems of only changing half of the plaintext block in one round and iterating for many rounds. In this article, a new logical combination method of generalized Feistel structure and ARX operations is proposed to improve the diffusion speed of ARX ciphers, called Shadow. Shadow overcomes the shortcomings of traditional ARX ciphers that only diffuse half of the block in one round. To ensure the efficiency of the encryption hardware circuit while ensuring the security of the physical-layer signal, we studied the round-based hardware architecture and the serial hardware architecture for Shadow cipher. Particularly, we conducted a series of performance tests on Shadow, including the avalanche effect, FPGA implementation, and ASIC implementation. Also, we conducted a security analysis of the Shadow. As shown by our experiments and comparisons, Shadow is compact in IoT nodes and is of high security against cryptanalysis.

In this era of pervasive computing, low-resource devices have been deployed in various fields. PRINCE is a lightweight block cipher designed for low latency, and is suitable for pervasive computing applications. In this paper, we propose new circuit structures for PRINCE components by sharing and simplifying logic circuits, to achieve the goal of using a smaller number of logic gates to obtain the same result. Based on the new circuit structures of components and the best sharing among components, we propose three new hardware architectures for PRINCE. The architectures are simulated and synthesized on different programmable gate array devices. The results on Virtex-6 show that compared with existing architectures, the resource consumption of the unrolled, low-cost, and two-cycle architectures is reduced by 73, 119, and 380 slices, respectively. The low-cost architecture costs only 137 slices. The unrolled architecture costs 409 slices and has a throughput of 5.34 Gb/s. To our knowledge, for the hardware implementation of PRINCE, the new low-cost architecture sets new area records, and the new unrolled architecture sets new throughput records. Therefore, the newly proposed architectures are more resource-efficient and suitable for lightweight, latency-critical applications.