Artificial Neural Networks (ANN) have proven to be effective in solving various emerging biomedical applications through specialized ANN hardware. Unfortunately, these ANN-based biomedical systems are increasingly vulnerable to both transient and permanent faults, potentially imposing serious threats to human well-being. Inspired by the self-healing and self-recovery mechanisms of the human nervous system, this paper seeks to address reliability issues of ANN-based hardware by proposing an Autonomously Reconfigurable Artificial Neural Network (ARANN) architectural framework capable of adapting its network structures and operations, both algorithmically and microarchitecturally, to react to unexpected errors. Specifically, we propose three key techniques - Distributed ANN, Neuron Virtualization, and Dual-Layer Checkpointing - to achieve cost-effective structural adaptations and facilitate accurate system recovery. Prototyped and demonstrated on a Virtex-5 FPGA, ARANN can cover and adapt 93% chip area (neurons) with less than 1% chip overhead and O(n) reconfiguration latency.

Cardiovascular disease (CVD) is the single leading cause of global mortality and is projected to remain so. Cardiac arrhythmia is a very common type of CVD and may indicate an increased risk of stroke or sudden cardiac death. The ECG is the most widely adopted clinical tool to diagnose and assess the risk of arrhythmia. ECGs measure and display the electrical activity of the heart from the body surface. During patients' hospital visits, however, arrhythmias may not be detected on standard resting ECG machines, since the condition may not be present at that moment in time. While Holter-based portable monitoring solutions offer 24-48 h ECG recording, they lack the capability of providing any real-time feedback for the thousands of heart beats they record, which must be tediously analyzed offline. In this paper, we seek to unite the portability of Holter monitors and the real-time processing capability of state-of-the-art resting ECG machines to provide an assistive diagnosis solution using smartphones. Specifically, we developed two smartphone-based wearable CVD-detection platforms capable of performing real-time ECG acquisition and display, feature extraction, and beat classification. Furthermore, the same statistical summaries available on resting ECG machines are provided.

To date, spike sorting for neural processing in brain-computer interfaces has been performed using off-chip analysis or custom ASIC designs. In this paper, we propose and test the feasibility of performing on-chip, real-time spike sorting on a commercially available and programmable smartdust wireless sensor network mote since such a platform is currently the closest to an implantable chip due to its small size and similar physical and environmental constraints.

Brain-computer interfaces (BCIs) offer tremendous promise for improving the quality of life for disabled individuals. BCIs use spike sorting to identify the source of each neural firing. To date, spike sorting has been performed using off-chip analysis, which requires a wired connection penetrating the skull to a bulky external power/processing unit, or ASIC designs, which lack the programmability to perform different algorithms and upgrades. In this research, we propose and test the feasibility of performing on-chip, real-time spike sorting on a programmable smartdust, including feature extraction, classification, compression, and wireless transmission. A detailed power/performance trade-off analysis using DVFS is presented. Our experimental results show that the execution time and power density meet the requirements to perform real-time spike sorting and wireless transmission on a single neural channel.

Motivated by excessively high benchmarking efforts caused by rapidly expanding design space and prevailing practices based on ad-hoc and subjective schemes, this paper seeks to improve simulation efficiency by proposing a novel methodology that combines two statistical analyses and one quantitative heuristic capable of subsetting a given benchmark suite based on the targeted processor configuration and desired variance coverage. We demonstrate the usage and effectiveness of the proposed technique by conducting a thorough case study on ImplantBench suite evaluating high/mid/low-end machine configurations modeled after three commercial embedded processors.

Continuously increasing demand for richer functionality, faster real-time communication, smaller feature size, longer battery life, more elevated security, and higher reliability is pushing the design for portable multimedia applications into the era where a single system is consisted of a general-purpose CPU interacting with several application-specific accelerating components and coprocessors to fulfill the ever diverse constraints imposed multi- directionally. The inter-component communication overhead, along with the engineering efforts required to integrate, verify, and validate such heterogeneous systems are scaled disproportionally as the complexity of such systems continue rising skyrocketedly. Moreover, due to limited instruction encoding space and the need to maintain backward compatibly in the future designs, designers are often forced to include only a very small subset of the total desired functionalities on chip, despite there can be more than sufficient silicon real estate to incorporate these specialized function units. This paper proposes a cost-effective technique of incorporating diverse functionalities into a single multi-purpose, streamlining acceleration unit, named Versatile Processing Unit (VPU), to replace the conventional ALU on a CPU. The proposed VPU can supply the general-purpose CPU with a rich set of streamlined operations, which may supersede some or even all of the heterogeneous cores. The superseded hardware components are removed to reduce the integration and communication overhead. The issues of limited instruction encoding space and future backward compatibility are resolved by our proposed dynamic instruction re-mapping technique, in which the instruction bit fields can be redefined on the fly to allow instruction space reuse at run time.

Power consumption, performance, area, and cost are critical concerns in designing microprocessors for embedded systems such as portable handheld computing and personal telecommunication devices. In previous work [A. Cheng et al., (2004)], we introduced the concept of framework-based instruction-set tuning synthesis (FITS), which is a new instruction synthesis paradigm that falls between a general-purpose embedded processor and a synthesized application specific processor (ASP). We address these design constraints through FITS by improving the code density. A FITS processor improves code density by tailoring the instruction set to the requirement of a target application to reduce the code size. This is achieved by replacing the fixed instruction and register decoding of general purpose embedded processor with programmable decoders that can achieve ASP performance, low power consumption, and compact chip area with the fabrication advantages of a mass produced single chip solution to amortize the cost. Instruction cache has been recognized as one of the most predominant source of power dissipation in a microprocessor. For instance, in Intel's StrongARMprocessor, 27% of total chip power loss goes into the instruction cache [J. Montanaro et al., (1996)]. In this paper, we demonstrate how FITS can be applied to improve the instruction cache power efficiency. Experimental results show that our synthesized instruction sets result in significant power reduction in the instruction cache compared to ARM instructions. For 21 benchmarks from the MiBench suite [M. Guthaus et al., (2001)], our simulation results indicate on average: a 49.4% saving for switching power; a 43.9% saving for internal power; a 14.9% saving for leakage power; a 46.6% saving for total cache power with up to 60.3% saving for peak power

Energy efficiency, performance, area, and cost are critical concerns in designing microprocessors for embedded systems such as portable handheld computing and personal telecommunication devices. This work introduces the concept of framework-based instruction set synthesis (FITS), which is a new instruction synthesis paradigm that falls between a general-purpose embedded processor and a synthesized application specific processor (ASP). FITS processors reduce code size and energy consumption by tailoring the instruction set to the requirement of a target application. This is achieved by replacing the fixed instruction and register decoding of a general purpose embedded processor with programmable decoders that can achieve ASP performance, low energy consumption, and smaller code size with the fabrication advantages of a mass produced single chip solution. Experimental results show that our synthesized instruction sets result in significant power reduction in the level one instruction cache compared to ARM instructions. The instruction cache is one of the most predominant sources of power dissipation on the processor. For instance, in Intel's StrongARM processor, 27 percent of total chip power loss goes into the instruction cache. For 21 MiBench benchmarks, our simulation results, indicate, on average, a 49.4 percent saving for switching power, a 43.9 percent saving for internal power, a 14.9 percent saving for leakage power, a 46.6 percent saving for total instruction cache power with up to 60.3 percent saving for peak power.

We propose a new instruction synthesis paradigm that falls between a general-purpose embedded processor and a synthesized application specific processor (ASP). This is achieved by replacing the fixed instruction and register decoding of general purpose embedded processor with programmable decoders that can achieve ASP performance with the fabrication advantages of a mass produced single chip solution.