Over the last decade the relative latency of access to shared memory by multicore increased as wire resistance dominated latency and low wire density layout pushed multi-port memories farther away from their ports. Various techniques were deployed to improve average memory access latencies, such as speculative pre-fetching and branch-prediction, often leading to high variance in execution time which is unacceptable in real-time systems. Smart DMAs can be used to directly copy data into a layer-1 SRAM, but with overhead. The VLIW architecture, the de-facto signal-processing engine, suffers badly from a breakdown in lock-step execution of scalar and vector instructions. We describe the Split Latency Adaptive Pipeline (SLAP) VLIW architecture, a cache performance improvement technology that requires zero change to object code, while removing smart DMAs and their overhead. SLAP builds on the Decoupled Access and Execute concept by 1) breaking lock-step execution of functional units, 2) enabling variable vector length for variable data-level parallelism, and 3) adding a novel triangular-load mechanism. We discuss the SLAP architecture and demonstrate the performance benefits on real traces from a wireless baseband-system (where even the most compute intensive functions suffer from an Amdahl’s law limitation due to a mixture of scalar and vector processing).

As the focus of networking research shifts from raw performance to the delivery of advanced network services, there is a growing need for open-platform systems for extensible networking research. The Applied Research Laboratory at Washington University in Saint Louis has developed a flexible network services platform (NSP) to meet this need. The NSP provides an extensible platform for prototyping next-generation network services and applications. The paper describes the design of a system-on-chip packet processor for the NSP which performs all core packet processing functions, including segmentation and reassembly, packet classification, route lookup, and queue management. Targeted to a commercial configurable logic device, the system is designed to support gigabit links and switch fabrics with a 2:1 speed advantage. We provide resource consumption results for each component of the packet processor design.

This paper develops a copy network architecture that can maintain the cell sequence integrity in multi-channel ATM switching. The architecture is internally nonblocking in the sense that the copying process of cells is constrained only by the availability of output channels. By using a relative ordering among the inputs, shared buffering, and a new switching paradigm called the nonblocking binary group network, we show how the cell sequence integrity can be maintained. Next, assuming the fanout request values of cells are distributed independently from cell to cell, we formulate a method of analyzing the performance of the copy network. This method uses the technique of tagged Markov chains to derive the stationary distributions for the number of cells in the copy network from which, delay, throughput, and cell loss probability can be accurately calculated as critical performance measures. We conduct a numerical study for the proposed architecture using this method wherein the effects of key network and traffic variables such as buffer and network sizes, and the mean and the variance of fanout request values are determined under arbitrary types of fanout distribution. Finally, we quantify the performance improvement due to fanout splitting which allows the fanout request from a single cell to be satisfied over multiple time slots.