Sanat Kamal Bahl

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1ranked-venue papers

1as first author

0since 2021 · last 2003

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems 1 paper		Reconfigurable computing and FPGAs · 100%
Computer networks 1 paper		Physical-layer communications · 50% Cellular and mobile networks · 50%

Topics — the 3 heaviest of 3, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Reconfigurable computing and FPGAs FPGA-based signal processing	1	2003	FPGA implementation of a fast Hadamard transformer for WCDMA · FPGA 2003
Physical-layer communications channel coding	1	2003	FPGA implementation of a fast Hadamard transformer for WCDMA · FPGA 2003
Cellular and mobile networks › 3g network WCDMA	1	2003	FPGA implementation of a fast Hadamard transformer for WCDMA · FPGA 2003

Methods — techniques the papers use, named apart from their topics

fast hadamard transform · 0.1

Year	Publication	Venue	Position
2003	FPGA implementation of a fast Hadamard transformer for WCDMA abstract In code division multiple access (CDMA) systems the base station identifies each user in a cell by unique orthogonal (Walsh) codes. The Walsh codes are generated at the transmitter using a Walsh-Hadamard function. A Fast Hadamard Transformer (FHT) is used at the receiver to decode the transmitted codes. The purpose of this study is to design a FHT which utilizes less hardware resources as compared to the existing designs and also suggest means for reducing the input length of the Walsh sequence. Our study results indicate that the FHT design using 16-chip sequence achieves 90% reduction in hardware resources (equivalent gate count) as compared to the design which uses 256-chip sequence. Also, the maximum frequency of operation of the 16-chip FHT (35.679 MHz) is more than double as compared to the 256-chip FHT (16.025 MHz). Sanat Kamal Bahl, James F. Plusquellic	FPGA	1