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Richard A. Stokes

dblp:12/2140 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1982
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Processor architecture and microarchitecture · 33% High-performance computing · 29% Memory systems · 29%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › memory architecture
interleaved memory		 0.011982
The Burroughs Scientific Processor (BSP) · IEEE Trans. Computers 1982
High-performance computing
supercomputing		 0.011982
The Burroughs Scientific Processor (BSP) · IEEE Trans. Computers 1982
Processor architecture and microarchitecture
vector processing		 0.011982
The Burroughs Scientific Processor (BSP) · IEEE Trans. Computers 1982
Compilers and program optimization › vectorization
vectorizing compiler		 0.011982
The Burroughs Scientific Processor (BSP) · IEEE Trans. Computers 1982
Parallel and multicore computing
parallel architecture		 0.011968
The ILLIAC IV Computer · IEEE Trans. Computers 1968
Reconfigurable computing and FPGAs › coarse-grained reconfigurable architecture
processing element array		 0.011968
The ILLIAC IV Computer · IEEE Trans. Computers 1968
Processor architecture and microarchitecture
SIMD		 0.011968
The ILLIAC IV Computer · IEEE Trans. Computers 1968

Methods — techniques the papers use, named apart from their topics

pipelining · 0.0crossbar switching · 0.0
YearPublicationVenuePosition
1982 The Burroughs Scientific Processor (BSP)
abstract
The Burroughs Scientific Processor (BSP), a high-performance computer system, performed the Department of Energy LLL loops at roughly the speed of the CRAY-1. The BSP combined parallelism and pipelining, performing memory-to-memory operations. Seventeen memory units and two crossbar switch data alignment networks provided conflict-free access to most indexed arrays. Fast linear recurrence algorithms provided good performance on constructs that some machines execute serially. A system manager computer ran the operating system and a vectorizing Fortran compiler. An MOS file memory system served as a high bandwidth secondary memory.
David J. Kuck, Richard A. Stokes
 IEEE Trans. Computers2
1968 The ILLIAC IV Computer
abstract
Abstract—The structure of ILLIAC IV, a parallel-array computer containing 256 processing elements, is described. Special features include multiarray processing, multiprecision arithmetic, and fast data-routing interconnections. Individual processing elements execute 4×106instructions per second to yield an effective rate of 109 operations per second.
George H. Barnes, Richard M. Brown, Maso Kato, David J. Kuck, Daniel L. Slotnick, Richard A. Stokes
 IEEE Trans. Computers6