Division is the highest latency arithmetic operation in present digital architectures and high-performance computing systems; as such drives the demand for efficient hardware division units. Accordingly, this paper proposes a novel architecture for a nonrestoring divisor based on the radix-2 signed-digit (SD2) representation. This notation has been chosen to achieve fast computation, as proposed by Avizienis (IEEE Transactions on Electronic Computers, vol. EC-10, no. 3, pp. 389-400, Sep. 1961), but the architecture presented in this paper, due to its structure and the definition of the cell implementing its architecture, saves area as well. The proposed divisor architecture is able to achieve a delay of order , similar to the solution presented by Takagi (IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, E89-A, no. 10, pp. 2874-2881, 2006) being considered as the state of the art, instead of other solutions that give growth. This is in line with the fact that even if our carry-chains have a less impact on the circuit the basic cell is larger compared to the one proposed by Takagi Our cells are larger that those proposed in literature, considering them as single circuit, but considering the overall structure there is a saving of some 40% in the number of gates and a gain of 55% in terms of power saving when compared with the state of the art.

A CMOS gate structure tolerating all single transistor stuck-at (TSA) faults and a large set of multiple faults is presented. Such structure is based on the simultaneous implementation of both the natural and the complemented form of the desired output; such implementation is easily modifiable to achieve fault tolerance and to obtain detectability of most of the faults which are not tolerated since they cause the two output lines to share the same value. Usually, production of the natural and complemented form of the output signal does not require one to double the number of transistors, thus resulting in cheaper (in terms of area) approaches.>

Design of multiple outputs CMOS combinational gates is studied. Two techniques for minimization of multiple output functions at the switching level are introduced. These techniques are based on innovative transistor interconnection structures named Delta and Lambda networks. The two techniques can be combined together to obtain further area reductions. Different synthesis algorithms are discussed, from exhaustive enumeration to branch and bound to heuristic techniques allowing to speed up the synthesis process. Simulation results for synthesis are introduced to compare the different algorithms. Design examples are also provided. Electrical simulations show that the dynamic behavior of such structures is comparable to the traditional static or domino implementations (obviously the new and traditional structures have the same static behavior).>

A scheme for a convolver design, called a multiparallel convolver, that is based on concurrent processing of p adjacent samples that are input simultaneously to the p-parallel convolver is presented. The scheme uses p units, each of which receives the input samples and produces one convolution every p samples; these are called p-phase subconvolvers. The detailed design of the p-phase subconvolvers and of the whole p-parallel convolver is presented and discussed. The scheme can be used for both the bit-parallel and the bit-serial input presentation of each sample. The input sample rate of the p-parallel convolver is p times the sample rate of a standard (1-parallel) convolver implemented using the same integration technology. The number of components required by a p-parallel convolver is approximately p times the number of components required by a standard convolver.>

The problem of mapping neural nets onto massively parallel architectures is considered. The solution examined, based upon regular array structures, can support the mapping of any neural graph. In particular, the case of feed-forward multilayered nets is analyzed, and is proven that in this case the mapping suggested is easily implemented and optimizes a number of relevant figures of merit. The structure of nodes, I/O ports, and switches is taken into account with reference to the neural net case. It is seen that the claims of inherent fault tolerance for neural nets are not actually kept for all classes of faults of a digital implementation; moreover, it is considered that end-of-production defects require restructuring to grant nominal initial operation. An efficient and straightforward solution to the defect-tolerance problem is presented, allowing the most limited redundancy versus good harvesting characteristics.>

In VLSI arrays, redundant cells are added as spares. The proposed approach is applicable as an offline technique at either production time and/or run time. Reconfiguration is implemented by index mapping using a sequence of two operators. A reconfiguration algorithm which utilizes index mapping is proposed. This algorithm uses a new approach to the assignment problem. It is shown that reconfiguration of fault-free cells is equivalent to a covering of faulty cells by spare cells. It is also established that in a two-dimensional array the optimal spare assignment is given by a maximum matching. This translates to a maximum flow. It is shown that a variation of the matching preserves the optimality of the assignment, while reducing the time complexity of the reconfiguration algorithm Characterization theorems for index mapping and simulation results to substantiate the practicality of the approach are presented.>

The authors present a novel approach to online error detection in an arithmetic array processor for very large computing applications. The use of redundant binary representation makes it possible to design strongly fault-secure architectures with respect to unidirectional stuck-at faults on multiple gate input and/or output lines. Online fault localization is also considered for fast array reconfiguration. Enhanced architectures have been proposed to identify the position of faulty elements in the regular array concurrently with the nominal computation. The proposed approach has been evaluated for a class of arrays which can be adopted in a wide spectrum of applications in digital signal and image processing and in matrix operations.>

A technique for reconfiguring an array of arbitrary rectangular shape from a fixed-size square array is presented. This type of reconfiguration is referred to as functional reconfiguration, as it maps processing functionalities (given by processing) into an array of dimensions different from those of the physical device. Functional reconfiguration is analyzed using index mapping. Locality and interconnection requirements are presented. Examples are given to illustrate the algorithm. It is also proven that the proposed technique achieves a lower intercell delay than previous techniques for certain values of ratio of the dimensions of the reconfigured rectangular array and the original square array.>

The paper presents the problem of fault tolerance in VLSI array structures: its aim is to discuss architectures capable of surviving a number of random faults while keeping costs (in terms of added silicon area and of increased processing time) as low as possible. Two different approaches are presented, both based upon introduction of simple patterns of faults and by global reconfiguration techniques (rather than one-to-one substitution of faulty elements by spare ones). Various solutions are compared, and relative performances are discussed in order to determine criteria for selecting the one most suitable to particular applications.

In 1981 a national research program for the design, simulation and construction of a multiprocessor image processing system was started. After a first phase devoted to the comparison of suggested and existing systems and to the definition of a set of benchmarks and to the evaluation of the performances of the major classes of machines, a new system has been defined. The structure of the new system is based on a pyramid of processors and many applications in which this machine may be exploited are highlighted. The multiprocessor architecture has been fully designed and the chip will be built by an Italian silicon. foundry, the SGS company, within the framework of the multichip national project.

This paper presents a technique for increasing the reliability of arithmetic units. An error model is then presented; this model we'll represents the faulty behavior of many arithmetic units. The Residue Number System and its related properties are used in order to obtain a simple architecture (called Reliability Network, R-Net). The main characteristics of the presented technique are a significant reduction in the number of gales and a limited increase of global execution times. The extensive use of combinational logic makes it possible to implement the R-Net almost completely by means of Programmable Logic Arrays (PLA's). Finally, both the intrinsic regularity of the R-Net and its simple internal interconnection scheme make this approach suitable for a practical VLSI implementation.

Two methods for performing binary-BCD conversion of positive integers are discussed. The principle which underlies both methods in the repeated division by five and then by two, obtained the first by means of substructions performed from left to right, the second by shifting bits before next subtraction. It is shown that these methods work in a time which is linear with the length in bit of the number to be converted. A ROM solution is proposed and its complexity is compared with that of other methods.

A family of four procedures to compute the inverse 1/X of a given binary number X normalized between 0.5 and 1 is described. The quotient is obtained in redundant binary form, i.e., in a base 2 code in which digits can assume any positive or negative integer value. All methods here described can be implemented by combinatorial networks; the dividers realized in this way are very fast because all carry propagations take place at the same time.

If a picture contains elongated objects of different thicknesses, one can make measurements on it which are thickness-invariant by first transforming it so that each object is thinned down to a "medial line" of constant thickness.Several algorithms are described which perform such a thinning transformation when applied to the picture in parallel.It is proved that these algorithms do not change the connectivity properties of the picture.