It is shown in the paper that Developmental Genetic Programming is an efficient tool for evolutionary development of intelligent supervisors that solve an extension of Resource-Constrained Project Scheduling Problem. The extension assumes that resources are only partially available. It also assumes that renewable resources affect the project cost. The cost should be as low as possible and a deadline of the project must be met. This is apparent with regard to software houses and building enterprises. Computational experiments showed that supervisors find solutions of the problem much faster than other genetic approaches. A specific property of the supervisor is that it has various strategies of allocating the resources to the tasks. The supervisor uses the strategies in order to develop a procedure for producing the best schedule for the whole project. The analysis of the evolutionary process was performed and experimental results were compared with the optimal ones obtained by means of the exhaustive search method.

In this paper, the use of Developmental Genetic Programming (DGP) for solving a new extension of the Resource-Constrained Project Scheduling Problem (RCPSP) is investigated.We consider a variant of the problem when resources are only partially available and a deadline is given but it is the cost of the project that should be minimized.RCPSP is a well-known NP-hard problem but in its original formulation it does not take into consideration initial resource workload and it minimises the makespan.Unlike other genetic approaches, where genotypes represent solutions, a genotype in DGP is a procedure that constructs a solution to the problem.Genotypes (the search space) and phenotypes (the solution space) are distinguished and a genotype-to-phenotype mapping (GPM) is used.Thus, genotypes are evolved without any restrictions and the whole search space is explored.The goal of the evolution is to find a procedure constructing the best solution of the problem for which the cost of the project is minimal.The paper presents genetic operators as well as GPM specified for the DGP.Experimental results showed that our approach gives significantly better results compared with methods presented in the literature.

A concept of artificial supervisor of multi-task realtime object-oriented system is introduced.Next, a procedure for automatic creation of artificial supervisors is presented.The procedure is based on developmental genetic programming.As an input data, UML diagrams are used.A representative example of creation of a supervisor of building a house illustrates the procedure.The efficiency of the procedure from various points of view and comparison considerations are given.

Scalability of data and throughput are important features of modern applications designed for distributed and loosely-coupled computer systems. In the paper, throughput scalable two-layer structures, called Throughput Scalability for SD2DS (TS2DS), are introduced. For maximum efficiency, the structures are stored in a distributed RAM of a multicomputer. Every data unit of TS2DS (a component) is split into two parts: a header and a body, located in distinct layers of the structure. For maximum flexibility, both layers are managed independently. Reference Counters are used to control the activity of the components and of the buckets. The most active components are mirrored to keep the throughput high. Two variants of the TS2DS, with different management of Reference Counters, are introduced and evaluated.

In the paper a resource-constrained project scheduling problem (RCPSP) aiming at project cost minimization is investigated. RCPSP is a well-known NP-hard optimization problem. A metaheuristic algorithm was adopted to solve the problem when applied to Critical Chain Project Management (CCPM). It starts with the initial schedule and searches for the cheapest solution satisfying given time constraints. A distributed version of the algorithm is proposed to reduce computation time. Independent processes on remote computers (workers) calculate different schedule modifications in the same time and send results back to a server. The server uses multithreading to distribute project data and search parameters to the workers. The number of workers used to achieve the best performance was estimated. The computational results of distributed processing showed high reduction of time needed to obtain the results, in comparison with centralized processing.

A new architecture of Scalable Distributed Data Structures (SDDS) is presented and evaluated. It applies for SDDS files with overactive servers. Every bucket of the file is supplemented with a reference counter. The number of references to a bucket is counted up. It reflects activity of the bucket and is used for selecting the most active and most often used buckets (overactive servers). Workloads of the servers are then balanced with the help of so called scalability of throughput. It is proven that this gives very good results for read-mostly databases, where extensive pattern matching takes place.

Many important problems that can be solved with theuse of computers require significant amount of various resources. A multicomputer could meet this requirement.However, such a system needs software and hardware supportto work efficiently. Scalable Distributed Data Structure(SDDS) is an application for a multicomputer that allowsfor efficient management of data. In the paper it is shownthat SDDS can be efficiently implemented on operationallevel of the multicomputer. Advantages and disadvantagesof such an approach are discussed. The main contributionof this paper is an architecture of SDDS for Linux-basedmulticomputer and its implementation. Results of performancetest for transactional database system which uses theimplementation are given, too.

In this work, a HW/SW iterative improvement co-synthesis algorithm, which allows for optimization of heterogeneous system architecture with dynamically reconfigurable FPGAs is presented. The algorithm maximizes speed of the system taking into consideration cost constraints.

High-level synthesis of PLD/EPLD-based systems is considered. Behavioral description of the system is formulated using procedural CHDL called UPLAND. The description is verified by simulation and tests are generated assuming a typical variable stuck-at fault model. Then, UPLAND source description is automatically translated into its corresponding target input format of a low logic level designing tool where target PLD/EPLD devices are optional. Finally, a fast state encoding optimization procedure is applied so that the nearly minimal PLD/EPLD-based implementation of the input format is obtained.>

A novel VLSI-oriented architecture to compute the discrete Fourier transform is presented. It consists of a homogeneous structure of processing elements. The structure has a performance equal to 1/t transforms per second, where t is the time needed for the execution of a single butterfly computation or the time needed for the collection of a complete vector of samples, whichever is longer. Although the system is not optimal (it achieves O(N/sup 3/ log/sup 4/ N) area*time/sup 2/ performance), the architecture is modular and makes it possible to design a system which performs FFT of any size without any extra circuitry. Moreover, the system can provide a built-in self-test and self-restructuring. The modular system is easy to integrate. Processing elements (PEs) are connected to the neighboring PEs only, and form a linear network easy to implement in two and three dimensions. The number of pins required for a chip does not depend on the number of PEs integrated on it, nor on the size of the transform. The system consists of only one type of integrated circuit with a structure irrespective of the transform size, which considerably reduces the cost of implementation.>

The paper presents two new versions of the FFT algorithm. Based on these versions a new VLSI oriented architecture for implementing of the FFT algorithm is introduced. It consists of a homogenous structure of processing elements. The structure has a performance equal to 1/t B transforms per second, where t B is the time needed for execution of a single butterfly computation. Besides high performance the architecture is modular and makes it possible to design a system which performs the DFT of any size with constant performance and without any extra circuitry. Moreover, the system can provide a built-in self test.