Robust object detection in adverse weather conditions is critical for ensuring the safety and reliability of autonomous driving systems. In this work, we present a detailed study on the adversarial robustness of YOLO-based detectors using the RealDriveSim dataset, which includes foggy, rainy, and nighttime scenarios. We benchmark YOLOv9 and YOLOv10 under clean conditions and observe high performance, with YOLOv10 achieving a mean average precision (mAP) of 69.6%. To evaluate vulnerability, we introduce an adversarial patch optimized to suppress road object detections. After patch-based perturbation, mAP drops to 44.3%, highlighting the importance of a defense system. To counter this degradation, we propose a lightweight LiDAR-camera fusion framework that does not require model retraining or architectural changes. Our method projects 3D LiDAR point clouds into the 2D image plane using intrinsic and extrinsic calibration parameters and cross-validates each 2D detection by checking for supporting 3D LiDAR points within its bounding box with an inference time of only 7.2 ms. Our fusion strategy effectively filters adversarial false positives, leading to a recovery in mAP to 62.9%, without requiring model retraining or architectural changes. To the best of our knowledge, this is the first work to benchmark adversarial robustness and sensor-level fusion defense on the RealDriveSim dataset, setting a new standard for evaluating real-world physical attack resilience in autonomous perception.

Machine learning (ML) has become essential for tasks like detection and classification in autonomous vehicles (AVs). However, ML models are vulnerable to adversarial attacks, which can weaken passenger trust and raise safety concerns in autonomous driving systems. This is especially critical in systems like traffic sign recognition (TSR), where a misclassification caused by an adversarial attack could lead to serious safety risks. This research work explored the vulnerabilities of TSR models to adversarial attacks focusing on projected gradient descent (PGD) and the fast gradient sign method (FGSM). An adversarial attack pipeline is proposed that leverages ScoreCAM-based region-of-interest (ROI) localization to enhance the effectiveness of these attacks. Adversarial attacks manipulate the input data to mislead the models, achieving a high attack success rate (ASR) by exploiting their vulnerabilities. Experimental results on multiple models such as VGG19, convolutional neural network (CNN), ResNet50 and vision transformers (ViT) demonstrate significant increases in ASR. For instance, our method achieved a 97.67% ASR using PGD on VGG19 and a 95.89% ASR using FGSM on the same model, marking a considerable performance gain over traditional approaches. Moreover, these results are achieved with high computational efficiency, with average query times as low as 69.8 milliseconds.

The increasing connectivity and integration of advanced technologies in vehicular systems have amplified the need for robust cybersecurity measures, particularly in heavy-duty (HD) vehicles, which are crucial to commercial transportation. Despite their importance, HD vehicles have received less attention in cybersecurity research compared to light-duty (LD) vehicles, leaving critical vulnerabilities unaddressed. This paper aims to bridge this gap by conducting a thorough analysis of the unique security challenges faced by HD vehicles. By comparing HD vehicles with LD vehicles, we identify distinct and vulnerabilities in two key areas: intra-vehicle networks and external connections. The study includes a comprehensive literature review focused on the cybersecurity of heavy- and medium-duty vehicles, through which we identify prevalent threats and potential mitigation strategies. This analysis underscores the necessity for enhanced protocol security and advocates for a detailed examination of both intra-vehicle networks and external connections.

In recent years, the automotive industry has increasingly recognized the importance of Threat Analysis and Risk Assessment (TARA) as a critical first step in cybersecurity planning. While standards such as ISO/SAE 21,434 provide a structured framework, they are primarily designed for light-duty vehicles and do not fully address the unique characteristics, operational environments, and vulnerabilities of heavy-duty (HD) commercial vehicles—despite their crucial role in public transportation, freight systems, and the supply chain. This study addresses that gap by customizing the ISO/SAE 21,434 risk assessment model specifically for HD vehicles. It employs a Multi-Criteria Decision-Making (MCDM) methodology to assign weights to the severity and feasibility criteria using expert input through the Fuzzy Analytic Hierarchy Process (FAHP). Expert-driven pairwise comparisons were conducted to evaluate the relative importance of each criterion separately for severity and feasibility assessment. The resulting model provides a tailored and robust approach for analyzing and assessing cybersecurity threats in HD vehicles, reflecting their distinct needs and risk profiles.

Binary polynomial multipliers impact the overall performance and cost of elliptic curve cryptography (ECC) systems. Multiplication algorithms with subquadratic computational complexity are widely used to reduce area requirements and improve the delay of ECC cryptographic hardware. This work presents an elliptic curve scalar point multiplication (SPM) processor implementation using a novel classification of improved overlap-free multipliers targeting applications in the Internet of Things (IoT) devices. The proposed multipliers combine the advantages of fewer partial products and the overlap-free reconstructions which results in better recurrence and improved performance. The proposed multipliers and point multiplication hardware were designed, implemented, and tested on FPGA. The implemented processor presents a reasonable trade-off between speed and area consumption, and the design compares favorably with the previous designs in terms of area-delay product.

Neuromorphic computers have been presented as alternatives to traditional von Neumann systems. Neuromorphic systems mimic neural structures of the human brain to make the energy-efficient and high-performance computations. This paper proposes high-speed with no DSP resources FPGA implementation of the SAM neuron model and its fully connected networks with random synaptic weights. The synthesis reports of the implemented SAM neuron with 50, 100, 500, 1000, 2000, 4000, 6000, and 8000 random inputs have been presented. Also, the results of the synthesized fully connected populations comprising 50, 100, 500, 1000, and 1500 SAM neurons have been reported. Accordingly, the FPGA synthesis results of the proposed spiking neuron and networks are noteworthy compared to the state of the arts in terms of performance and DSP resources.

A new and efficient Hodgkin–Huxley (HH) neuron has been implemented on field-programmable gate array (FPGA). Multiplication, division, and exponential terms were implemented using the COordinate Rotation DIgital Computer (CORDIC) algorithm with carefully selected iteration numbers for each operation to greatly reduce the hardware resource requirements while simultaneously maintaining system throughput and a maximum clock frequency of over 275 MHz. The proposed design achieves higher modeling accuracy than previously proposed designs and an accuracy-resource trade-off that represents dramatic improvements. Additionally, all the neuron’s physiological parameters are variable as inputs to the proposed design postimplementation for a high degree of freedom in neuroscientific simulations. The implemented neuron is presented with results, and the behavior of the implemented system is evaluated to verify its close behavioral matching to the target neuron model.

Novel binary polynomial multipliers have been designed using M-term overlap-free Karatsuba multiplication (OFKM), where$M$is 5–8. The proposed designs were realized in digital hardware and implemented on field-programmable gate array (FPGA) and the best value of$M$was selected and presented for common National Institute of Standards and Technology (NIST) operand sizes from 64 to 571 bits. The implemented hardware designs use a hybrid approach that combines a given M-term overlap-free Karatsuba multipliers with two-term splitting to reduce the need for zero-padding in the final recurrent stages. Compared to the traditional M-term Karatsuba multipliers, the proposed overlap-free implementations offer reductions in delay and area-delay product (ADP). The proposed designs also compare favorably to previous implementations of binary polynomial multipliers. Their favorable characteristics make the proposed overlap-free Karatsuba polynomial multipliers viable options for use in cryptographic systems where speed is a significant consideration and hardware resource consumption must be limited.

The concept of input sparsity in Spiking Neural Networks for pattern recognition is introduced and explored with the goals of reductions in network inference time and size, leading to lower resource requirements in hardware implementations. A method is proposed by which selective input sparsity can be inferred from the training set to reduce the size of the network before training and decrease the network inference time. This method also requires no additional pre-processing steps during the testing phase, making it an excellent candidate for edge applications. For a basic fully connected spiking neural network trained to solve the MNIST handwritten digits, selective input sparsity is applied and the network size is reduced by 58.16% and a 41.07% decrease in the network's inference time is observed without notable accuracy hinderance. In the case of the Fashion MNIST dataset, selective input sparsity reduced the network size by 55.99% and reduced the network's inference time by 59.05%.

In the above article[1], in the title of the article, the acronym FPGA was incorrectly used as FGPA. The correct title should be “An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FPGA Implementation.”

The increasing concern about the security and reliability of abroad manufactured integrated circuits (ICs) has attracted academia and industries to develop hardware Trojan (HT) detection approaches. This article presents an efficient integrated HT detection technique based on evaluating changes in the integrated parasitic capacitors. The HT detection circuit consists of a capacitively coupled, low-power, low-noise, operational transconductance amplifier (OTA), which can detect capacitance fluctuations in the range of 10 aF. The HT detection circuit consumes$5.88~\mu \text {W}$from 1.8-V power supply in 180-nm CMOS technology. The detection method is based on clustering the IC and monitoring each cluster’s flag. The flag set circuit is designed to sense parasitic capacitance and change its status based on it. The proposed technique can detect the HT circuit before the activation of the IC. Moreover, this technique shows very promising results in detecting HTs with zero-delay effect, which is a challenging issue in the conventional delay-based side-channel signal analysis method. More significantly, the proposed method does not require a golden IC for HT detection and can detect the HT using simulation-based data. The proposed method creates a recognizable difference detection signal between the capacitive behavior of an infected and a pure IC. This results in a high confidence level in the proposed detection method. The proposed idea is implemented on ISCAS’85 benchmark circuits, and the detection outcomes and the statistical simulations are presented.

Finite field multiplication is a fundamental and frequently used operation in various cryptographic circuits and systems. Because of its high complexity, this operation generally determines the overall complexity and cost of these systems. Therefore, finite field multipliers and their hardware implementation have received considerable attention from researchers. This article proposes a methodology to design an efficient Galois field multiplier. First, space and time complexities for theoretical and field-programmable gate array (FPGA) implementations of M-term Karatsuba-like finite field multipliers were obtained. In addition, an algorithm was developed to obtain an efficient design based on a composite M-term Karatsuba-like multiplier. Furthermore, the proposed multipliers were verified and implemented on various FPGA devices, and implementation results were presented. Reported device utilization and latency indicated that the proposed multiplier is roughly 26% faster and 15% more efficient in the area–delay product compared to the standard Karatsuba multiplier. Moreover, comparison with state of the art also indicated that the proposed design is leading in terms of effectiveness and speed.

Cryptography systems have become inseparable parts of almost every communication device. Among cryptography algorithms, public-key cryptography, and in particular elliptic curve cryptography (ECC), has become the most dominant protocol at this time. In ECC systems, polynomial multiplication is considered to be the most slow and area consuming operation. This article proposes a novel hardware architecture for efficient field-programmable gate array (FPGA) implementation of Finite-field multipliers for ECC. Proposed hardware was implemented on different FPGA devices for various operand sizes, and performance parameters were determined. Comparing to state-of-the-art works, the proposed method resulted in a lower combinational delay and area-delay product indicating the efficiency of design.

A physical unclonable function (PUF) is a promising lightweight circuit that provides security and authentication capability for electronic devices with low computational resources. Among various PUFs, the bistable ring PUF (BR-PUF) is considered one of the robust configurations. However, it has been shown that the challenge-response pairs (CRPs) from BR-PUF are vulnerable to statistical machine learning (ML) attacks, such as k-junta learning, support vector machine (SVM), and logistic regression (LR). In this article, we first show that the k-junta attack can break CRPs from the BR-PUF. Then, we present a hybrid chaotic-BR-PUF structure that obfuscates the BR-PUF response with the nonlinearized chaotic response. The proposed PUF structure has been implemented and experimentally evaluated on Xilinx Artix-7 FPGA, and the PUF measurements were captured. The proposed PUF was tested with a powerful statistical method developed using k-junta-based learning to confirm its strength against such attacks and evaluated using CRPs collected. The proposed PUF provides better resistance against ML attacks and reduces the learning accuracy to 50%–60% compared with previously proposed PUFs.

This work presents mathematical modifications to the Izhikevich Spiking Neuron Model to allow for a simple, low-area digital hardware implementation of a spiking neuron with similar behavioural characteristics and low computational intensity. The implemented neuron circuit only requires one input operational parameter to replicate all of the cortical neuron behaviours described by Izhikevich.

In this paper, the optimized design strategies for the implementation of a CMOS digitally controlled oscillator (DCO) are investigated. Moreover, the boosting mechanism for a DCO with and without negative resistance is considered. The proposed design methodology is based on an in-depth mathematical analysis of the startup condition and amplitude of oscillation. This approach results in an optimized topology for a Colpitts Clapp-DCO (CC-DCO). The improved performance is achieved through the negative resistance boosting mechanism. The negative resistance enhances the startup time and increases amplitude stabilization across a wide tuning range (TR). Moreover, it improves the phase noise (PN) performance while suppresses the amplitude-to-phase conversion. The proposed 24-GHz CMOS enhanced CC-DCO (ECC-DCO) is implemented in 65-nm TSMC CMOS process. It can effectively reduce the startup time by 41%. Also, it boosts and stabilizes the amplitude across a TR of 29%. The amplitude varies by 1.5% across the 22-29-GHz TR. The ECC-DCO consumes 12.8 mW. It shows a PN of -106 dBc/Hz at 1-MHz offset frequency and achieves -185-dBc/Hz figure of merit (FoM) and -194-dBc/Hz FoM for tuning.

In this paper, a mixed-signal current-mode structure of a feed-forward neural network is implemented. In this network, neurons are divided and distributed as sub-neurons into parallel elements composing unified synapse-neuron building blocks in combination with the synapses. Although in this brief paper a resistive sigmoidal neuron is considered, the neuron is adaptable to other forms of transfer functions. The synapse structure employs AND gates in addition to weighted current mirrors to reduce the area of the design. As a proof of concept, a 4-3-2 CMOS-based network is implemented. The average and maximum power consumptions of the network are 0.93mW and 5.81 mW respectively. The area of the entire network is measured 142299.5μm2. The network was successfully tested with a series of sample patterns.

In this paper, the design and implementation of an analog sigmoid neuron is presented. The activation function of the proposed neuron is implemented based on the piecewise linear approximation in the analog domain. The proposed neuron provides the required accuracy that cannot be achieved in general by analog neural network implementations. General digital outputs of a sigmoid neuron are replaced with fewer analog digits of the continuous valued number system (CVNS), while at the same time maximum approximation error is kept the same as the digital architectures. The proposed CVNS neuron resulted in an optimal ASIC implementation and is suitable for neurochips with on-chip learning. The VLSI implementation of the neuron is carried out using current-mode circuits. The implementation results compare favorably with previously developed structures in terms of area, delay, and power consumption. The proposed neuron structure occupies 28% less area compared with the state-of-the-art methods and it has two times lower power × delay.

Astrocyte as one of the brain cells controls synaptic activity between neurons by providing feedback to neurons. A novel digital hardware is proposed for neuron-synapse-astrocyte network based on the biological Adaptive Exponential (AdEx) neuron and Postnov astrocyte cell model. The network can be used for implementation of large scale spiking neural networks. Synthesis of the designed circuits shows that the designed astrocyte circuit is able to imitate its biological model and regulate the synapse transmission, successfully. In addition, synthesis results confirms that the proposed design uses less than 1% of available resources of a VIRTEX II FPGA which saves up to 4.4% of FPGA resources in comparison to other designs.

This paper presents a CMOS 24GHz Clapp-Colpitts Digitally Controlled Oscillator (CC-DCO) with 22GHz-29GHz tuning range that is able to address Short Range Radar (SRR) requirements. In order to overcome the major challenge to design a wide tuning range DCO, proper oscillator topology is chosen, specific tuning mechanism is implemented, and design optimization strategies are employed without degrading the Phase Noise (PN) performance. The CC-DCO is implemented with 65nm CMOS process. A wide tuning range of 29% and a fine tuning step of 1.6 MHz are achieved simultaneously. The CC-DCO consumes 10mA from a 1V supply. It shows a PN of -187dBc/Hz at 1 MHz offset frequency, and achieves -268dBc/Hz figure of merit considering the tuning range.

In this paper an analog cellular neural network is proposed with application in physical unclonable function design. Dynamical behavior of the circuit and its high sensitivity to the process variation can be exploited in a challenge-response security system. The proposed circuit can be used as unclonable core module in the secure systems for applications such as device identification/authentication and secret key generation. The proposed circuit is designed and simulated in 45-nm bulk CMOS technology. Monte Carlo simulation for this circuit, results in unpolarized Gaussian-shaped distribution for Hamming Distance between 4005 100-bit PUF instances.

In this paper design and implementation of a modular mixed-signal feed-forward neural network is presented. The network is implemented based on the Continuous Valued Number System (CVNS) arithmetic with neurons distributed in the network. Synapse weights are implemented on the chip using capacitive analog memories. Weight values are stored as the CVNS values and are refreshed and updated using the overlap between the CVNS digits. Current-mode logic is used for implementation in order to simplify the circuit design, and especially addition, which resulted in reduced power and area consumption. The distributed nature of the neurons allows for expansion of the network into larger networks. Individual modular layers are fabricated in TSMC CMOS 180nm, and are used to form different network sizes. The module is used to configure two proof of concept examples, a 2 - 2 - 1 and a 3 - 2 - 1 network to solve the XOR problem. Results of test and verification presented in this paper show the network flexibility of the proposed design to form various network configurations.

Designing low noise-to-signal-ratio (NSR) structures is one of the main concerns when implementing hardware-based neural networks. In this paper, a new continuous valued number system (CVNS) multiplication algorithm for low-resolution environment is proposed with accurate results. Using the proposed CVNS multiplication algorithm, VLSI implementation of a high-resolution mixed-signal CVNS synapse multiplier for neurochips with on-chip learning is realized. The proposed CVNS multiplication algorithm provides structures with lower NSR. Therefore, the proposed CVNS multiplication algorithm can be exploited to design robust CVNS Adaline for neurochips with on-chip learning.

The finite precision of inputs and weights in analog implementation of neural networks degrades the output response. The output response degradation is modeled by Noise-to-Signal-Ratio (NSR). Furthermore, neuron×NSR is an indicator of structure efficiency. In this paper, a new lumped Madaline architecture for networks with a large number of inputs and high input and weight variation is proposed. The information redundancy present in Continuous Valued Number System (CVNS) is exploited to improve the NSR. Moreover, the mathematical analysis of the NSR of Madalines based on previously developed structures and the proposed structure is conducted. The comparison shows that the proposed structure compares favorably to previously developed lumped architectures in terms of NSR and neuron×NSR.

Nonlinear activation function is one of the main building blocks of artificial neural networks. Hyperbolic tangent and sigmoid are the most used nonlinear activation functions. Accurate implementation of these transfer functions in digital networks faces certain challenges. In this paper, an efficient approximation scheme for hyperbolic tangent function is proposed. The approximation is based on a mathematical analysis considering the maximum allowable error as design parameter. Hardware implementation of the proposed approximation scheme is presented, which shows that the proposed structure compares favorably with previous architectures in terms of area and delay. The proposed structure requires less output bits for the same maximum allowable error when compared to the state-of-the-art. The number of output bits of the activation function determines the bit width of multipliers and adders in the network. Therefore, the proposed activation function results in reduction in area, delay, and power in VLSI implementation of artificial neural networks with hyperbolic tangent activation function.

This paper presents the design and implementation of a multiple-valued adder, with application in smart cards and cryptographic processors. The adder is designed based on the principles of truncated Continuous Valued Number System (CVNS), in order to relax the implementation requirements of the circuit topology and designs. The CVNS adder has an almost constant power consumption, independent of the input values. This feature makes this adder immune against side channel attacks, which may use the power consumption pattern to obtain the intermediate values of arithmetic operations.

An important part of any hardware implementation of artificial neural networks (ANNs) is realization of the activation function which serves as the output stage of each layer. In this work, a new NMOS/PMOS design is proposed for realizing the sigmoid function as the activation function. Transistors in the proposed neuron are biased using only one biasing voltage. By operating in both triode and saturation regions, the proposed neuron can provide an accurate approximation of the sigmoid function. The neuron circuit is designed and laid out in 90-nm CMOS technology. The proposed neuron can be potentially used in implementation of both analog and hybrid ANNs.

Distributed Neural Networks (DNNs) are generally providing self-scaling property together with higher noise immunity for resistive-type neural networks. Continuous Valued Number System (CVNS) is a potential candidate to build the DNNs; however, implementation of a CVNS digit in its complete form needs a high resolution environment which is not practical. Truncation methods are applied to CVNS digits to make them adaptable to the low resolution environments. However, truncated CVNS operations may decrease the accuracy and immunity to noise compared to the complete CVNS operations. In this work, a truncated CVNS DNN is proposed, and studies over Noise to Signal Ratio (NSR) and accuracy are provided. Studies show that the accuracy is acceptable, and the NSR is still less than the NSR of conventional DNNs.

Multi-valued dynamic memories are appropriate for applications such as implementation of neural networks, where massive number of synaptic weights have to be stored on a chip. In this paper, a novel storage and refreshing configuration to store up to 4 bits (16 levels) per cell on a dynamic memory is proposed. This configuration is based on the Continuous Valued Number System (CVNS). Error correction method according to the CVNS properties is used in order to increase the noise margin of memory cells. Furthermore, by decreasing the leakage current, the refresh cycle time is increased. The circuits are designed, simulated, and finally laid out using 90-nm CMOS technology.

In order to optimally set up and configure an analog neural network in system-level, fundamental issues such as accuracy, robustness, function smoothness and minimality has to be considered. This paper focuses on choosing optimal Continuous Valued Number System (CVNS) neural networks, and shows using system-level analysis that how CVNS networks can be used to implement large size networks. The network is implemented using analog non-linear activation function with more precision, and provides more accuracy in comparison to analog networks. The CVNS computation system which is used as an alternative method of implementation, is analog in nature and employs digit-level analog modular arithmetic. The information redundancy among the digits can be used to increase the accuracy of the precision using analog circuitry with arbitrary accuracy. Moreover, the system configuration take advantage of distributed neuron properties. This type of neurons reduce overall network sensitivity to mismatches that are inherent in any neural networks implemented by analog circuitries. Moreover, to reduce the network complexity in terms of number of interconnections, a series configuration of multiplexer and demultiplexer is used. Weights are refreshed and refined as an overall approach to maintain the weights stored on chip, and are not used to compute network response. To study overall accuracy of the system, stochastic modeling of the network is carried out. The proposed network has comparable sensitivity to other CVNS Madaline, while reduces the network complexity in terms of reducing computing units and interconnections proportional by a factor proportional to the network nodes.

In this paper, a multiple-valued DRAM is proposed. Error correction has been used to increase the noise margin of the system. The refresh system is based on series configuration of A/D and D/A converters for each data line. The A/D converters are based on a modular reduction operation, which provides an area efficient design. This memory cell can be used in hardware implementation of multiple valued neural networks.

This paper explores properties of an analog artificial neural network architecture based on Continuous Valued Number System (CVNS) with distributed neurons. In conventional lumped neural networks, the effect of weight quantization errors effects the performance of the network as the network size increases. However, based on a stochastic model it is shown here that the CVNS capability in detecting and correcting errors along with the inherent self-scaling property of distributed neurons, can control the output quantization noise to signal ratio. This property contributes to a robust analog VLSI architecture based on analog distributed CVNS-Adaline neurons.

In this paper, design of a mixed-signal 64-bit adder based on the continuous valued number system (CVNS) is presented. The 64-bit adder is generated by cascading four 16-bit radix-2 CVNS adders. Truncated summation of the CVNS digits reduced the number of required interconnections in the system, which in turn reduced design complexity and hardware costs. This adder can perform one 64-bit, two 32-bit, four 16-bit, or eight 8-bit additions on demand for media signal processing applications. The compact and low-power and low-noise design of the adder is suitable for this type of application. The 64-bit adder designed in TSMC CMOS 0.18-mum technology, has a worst case delay of 1.5 ns, energy dissipation of about 14 pJ with the core area of 13 250mum2.

Binary multiplication is one of the fundamental arithmetic operations, and it is used in digital filters and signal processing applications. The Continuous Valued Number System (CVNS) is a recently introduced number system that allows digital arithmetic, with arbitrary precision, to be implemented with analog circuitry. Due to the analog nature of the numbers system, CVNS reduces the total system and cross talk noise. An8×8digital multiplier is proposed, using CVNS compressors for reducing the digital partial products. A new definition for the CVNS compressor for the first time is introduced, along with a novel CMOS current mode circuit. The multiplier is realized in TSMC CMOS0.18μmtechnology, with a maximum delay of900ps, static power consumption of19mWand a core area of11200μm2. The example demonstrates that CVNS designs can yield fast, low power arithmetic circuits using low noise analog circuitry.

A new mixed-signal feed-forward neural network for pattern/shape recognition problems is proposed. The network has a mixed-signal structure, operations are performed in analog and weights are stored in digital. To increase the network robustness, on-chip training with Madaline Rule III is used. The proposed architecture uses time-multiplexing to increase the network density and resistive-type neurons for their self-scaling property. The results of an XOR network are presented to test the network.