This article consists of a collection of slides from the author's conference presentation.

Package-level integration using multi-chip-modules (MCMs) is a promising approach for building large-scale systems. Compared to a large monolithic die, an MCM combines many smaller chiplets into a larger system, substantially reducing fabrication and design costs. Current MCMs typically only contain a handful of coarse-grained large chiplets due to the high area, performance, and energy overheads associated with inter-chiplet communication. This work investigates and quantifies the costs and benefits of using MCMs with fine-grained chiplets for deep learning inference, an application area with large compute and on-chip storage requirements. To evaluate the approach, we architected, implemented, fabricated, and tested Simba, a 36-chiplet prototype MCM system for deep-learning inference. Each chiplet achieves 4 TOPS peak performance, and the 36-chiplet MCM package achieves up to 128 TOPS and up to 6.1 TOPS/W. The MCM is configurable to support a flexible mapping of DNN layers to the distributed compute and storage units. To mitigate inter-chiplet communication overheads, we introduce three tiling optimizations that improve data locality. These optimizations achieve up to 16% speedup compared to the baseline layer mapping. Our evaluation shows that Simba can process 1988 images/s running ResNet-50 with batch size of one, delivering inference latency of 0.50 ms.

We describe a network sharable, interactive computational tool for rapid and sensitive search and analysis of biomolecular sequence databases such as GenBank, GenPept, Protein Identification Resource, and SWISS-PROT. The resource is accessible via the World Wide Web using popular client software such as Mosaic and Netscape. The client software is freely available on a number of computing platforms including Macintosh, IBM-PC, and Unix workstations.

As networks approach gigabit performance, supercomputer host interfaces are becoming the communication bottleneck.The Network Interface Unit (NIU) is a highperformance host interface for Pixel Planes 5, a custom graphics supercomputer.The design offers both performance and programmability through a balance of ahtamarshaling hardware and an embedded processor.In this paper, we describe the NW hardware and jirmware architecture.We present some prelitw"nary peq$ormance measurements and assess the applicability of this design for the targeted environment.We also comment on its suitability for other environments and outline plans for the future work.PemnissiOn to copy witkut fee df or pan of Ibis mat.xial is gmntaf, pmvikd that tbe copie6 are not made or diswilmted for direct commercial adva"lage, the ACM copyright nctice and ibe tide of the publication and 124 its date appear, and notice is given that copying is by permission of tbe Assxiation for Commting Machinery.To copy otbenvise, or to repubkb, requires a fee andkr specific permission.