An accurate and efficient parameter extraction methodology, utilizing a new technique called recursive inverse approximation (RIA), is proposed for statistical modeling of integrated circuits. The main features of RIA are (1) linear approximation is used to obtain initial model parameter estimates, (2) reverse verification performs accuracy checking, and (3) error correction functions are constructed in the extracted parameter space to recursively refine the previously extracted parameter values. As a result, an approximate inverse mapping from the measured performance space to the model parameter space is established for statistical parameter extraction. Examples of parameter extraction for MOS transistors and IC multiplier block demonstrate high efficiency and accuracy of the new method.

A new performance measure, based on the capability indices C/sub p/ and C/sub pk/ (commonly used in process control), is proposed for general circuit Design for Quality. It overcomes some of the critical limitations of the traditional quadratic loss function (e.g., that of Taguchi) and leads to the creation of a new methodology for statistical circuit design. It also allows for the automation of the manual two-stage variability minimization/tuning methodology, and gives a concrete interpretation to the "goodness" of a circuit in easy to understand terms. Successful IC variability/performance optimization examples are presented.>

A methodology for statistical characterization and modeling of analog functional blocks, including inter-block and intra-block correlations is presented in this paper. The functional blocks are statistically characterized in the proposed model by a small number of postulated random variables. The related model parameter extraction is described. An OTA-C filter is used to demonstrate the proposed modeling method. Very good agreement with the Monte Carlo circuit analysis was obtained.>

An interpolation scheme (maximally flat quadratic interpolation (MFQI) and an approximation scheme (group method of data handling (GMDH)) are combined to obtain a novel heuristic approximation method. This composite structure overcomes the shortcomings of the individual methods while maintaining their desirable features. The combined method is efficient and much more accurate than either of the two individual schemes. This is the case especially when the functions being approximated are complex within the input variable range specified. Several analog and digital circuit examples, in addition to a variability minimization example for a delay circuit, demonstrate the utility of the proposed approach.>

A generalized formulation of the drift reliability optimization problem is presented. Algorithmic solutions are also proposed. They can be implemented readily in the existing circuit optimization environments and applied to integrated circuit design. Such applications are demonstrated, considering degradations due to hot electron effects. The results show that the proposed approach can significantly increase long-term circuit reliability and increase its robustness.>

The authors present several novel results in the area of variability minimization. They develop a variability gradient formula, give the theoretical conditions for variability minimization, and outline the principles and practical solutions of factor screening for variability. A multistage procedure is described for on-target design, based on variability gradient information, dynamic screening, performance variance minimization, and separate on-target tuning. This methodology was successfully applied to the variability minimization of a practical CMOS delay circuit, after several direct methods of on-target oriented methods failed.>

A relationship between yield optimization, deterministic minimax design, and the Taguchi 'on-target' design with variability reduction is established. It is shown that all these and other design approaches can be combined into one coherent methodology, using the same statistical optimization algorithms and the same generic gradient evaluation formulas. A specific choice is controlled by the selection of the generalized membership function w(.) of the acceptability region, and a sequence of the values of the smoothing parameter beta . Moreover, any 'intermediate' approach between the basic types introduced can be defined in a sense similar to the one used in Zadeh's (1968) fuzzy set theory. As a result, circuit quality can be optimized within the same basic methodology, using different design strategies and investigating different trade-offs, e.g., between the performance and yield. Test examples, as well as a practical CMOS circuit are investigated. Convolution smoothing techniques, and the stochastic approximation approach to statistical optimization are utilized.>

A method of yield derivative estimation for nondifferentiable or truncated probability-density functions (PDFs) is proposed and applied to yield optimization. The method applies convolution techniques and is based on the recently introduced perturbation approach. It constructs some approximation to the original PDF and requires a small number of samples per yield-optimization-algorithm step. The method is efficient and provides fast convergence in the solution, especially for problems of high dimensionality. Several yield-gradient estimation formulas are given. Some theoretical and practical aspects of the proposed method are discussed. Practical applications are demonstrated on several analog filters, and the method is compared with some other existing methods.>

An approach to statistical design centering (SDC) based on a simple generalization of the production yield concept is introduced, leading to a new figure of merit called the "income index." The measure can be considered as a simple model of the manufacturer's income or as a parameter characterizing the average quality of the manufacturing process. The income index takes into account the "price" (or "quality") decrease of inferior and the "price" (or "quality") increase of superior designs. The method is especially effective in improving quality of the designs characterized by large production yield. It can also handle the problems where the circuit specifications are negotiable or not exactly known, thus extending the area of SDC applications. For the implementation of the proposed method the existing gradient algorithms of yield optimization can be used after only minor modifications of gradient calculating subroutines and practically negligible additional computational costs.

In this paper theoretical possibilities of statistical yield gradient estimation are discussed for those cases where circuit element probability density functions are truncated or nondifferantible, with a uniform distribution being a special case. With the yield gradient information available, the efficient derivative methods of yield optimization can be used. General derivative formulas are developed and their intuitive and geometric interpretations are given. Relationship between the yield derivatives and the marginal density functions of "pass" (or "fail") points is shown. Two possible algorithms for yield derivative estimation are discussed. The theory developed is also used to provide insight into some other methods of yield optimization.

Algorithms, software tools and the relevant methodology for production yield optimization with respect to fundamental technological parameters of the IC manufacturing process (such as diffusion times and temperatures) and element layout mask dimensions are discussed. The tools developed include: STOCH-PAC--a package of new yield optimization and yield gradient estimation algorithms based on Stochastic Approximation approach and the Method of Random Perturbations; YIELD-PAC - a package of yield evaluation subroutines providing an interface to SPICE-PAC circuit simulation package; FABPAC - an interface to the FABRICS statistical process simulator; and IRIS (Interactive Restructurable Interface System)--a flexible user interface for efficient data manipulation, creation of different design tasks and macrotasks, restructuring the set of active subroutines, etc. These tools have been integrated into the TOY (Technological Optimization of Yield) program. Examples of yield optimization with respect to process parameters and layout dimensions using TOY are given.