A three-dimensional (3-D) integration technology based on the wafer-to-wafer bonding using through silicon vias (TSV's) has been developed for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have proposed a new reconfigurable parallel image processing system. To achieve this system, we have proposed a new 3-D integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration.

High density through silicon via (TSV) is a key in fabricating three-dimensional (3-D) large-scale integration (LSI). We have developed polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly-Si TSV technology for 3-D integration. In the poly-Si TSV formation, low-pressure chemical vapor deposition poly-Si heavily doped with phosphorus was conformally deposited into the narrow and deep trench formed in a Si substrate after the surface of Si trench was thermally oxidized. In the W/poly-Si TSV formation, tungsten was deposited into the Si trench by atomic layer deposition method after the poly-Si deposition, where poly-Si was used as a liner layer for W deposition. The 3-D microprocessor test chip, 3-D memory test chip, 3-D image sensor chip, and 3-D artificial retina chip were successfully fabricated by using poly-Si TSV.

In order to achieve human-like quick eye movements and image processing for intelligent mobile robots, a high speed vision system is developed. The vision system is composed of a binocular camera head and high speed image sensors. The camera head is originally designed to mount neuromorphic vision chips fabricated using three-dimensional integration technology. The prototype of the neuromorphic vision chip has three layers: (1) photoreceptor layer, (2) horizontal and bipolar cell layer, and (3) ganglion cell layer. An image sensor is separately developed, which corresponds to the photoreceptor layer of the layered vision chip. The image sensors are tentatively mounted on the camera head, since the resolution of the prototype of the layered vision chip is not sufficient at this stage. The camera head has an azimuth DOF for each eye and a common elevation DOF. The weight of the camera head is strictly limited, since it is mounted on a mobile robot. In order to satisfy both demands for the quick movements and light weight, the camera head is designed based upon a simple parallel mechanism. The total performance of the vision system is examined in this work. Saccadic eye movement and frequency response are experimentally reviewed

We propose a novel real-shared memory module with multiports which is called "RSMM" to overcome the bus bottleneck problem in a parallel processor system with shared memory. The testing processor can be directly connected to this RSMM via its multiport interface without conventional common bus. It is the characteristic of the design to utilize the high bandwidth "multiport ring-bus" architecture in order to achieve high speed data transfer inside the RSMM. The RSMM has 8 ports. Therefore it can provide data sharing for 8 peripheral equipments (PE) simultaneously. The peak of the transfer throughput can achieve 3.2 Gbytes/s. The basic operation of the RSMM is confirmed by simulation and the result shows that the system performance with the RSMM is superior to that with conventional common buses.

A parallel images processing field programmable gate array (FPGA) for real time image processing system has been proposed to realize high image processing speed and flexibility. This FPGA has a small size configuration memory. In addition, a parallel reconfigurable interconnection network and logic blocks have been used in this FPGA. A test chip was designed and fabricated using 0.35 /spl mu/m CMOS technology. It was confirmed in the test chip that the reconfiguration of the image processing is successfully performed.

Every year, the design and EDA communities are besieged by dire warnings about the impending doom of "design as we know it." Every year, another unpleasant physical effect from the evil depths of deep submicron physics surfaces, compromising our designs in new and vile ways. Every year, the same story: more nanometer woes. Rather than endorse a new winner in this year's race for the next worst thing from the nanometer arena, this panel gathers a set of world-class technology experts to debate what effects are hiding just around the next corner, waiting to pounce on the unwary tool or chip designer. Which among these is really the most important, when will it happen, and why.

The smart VISIOn chip has a large potential for application in general purpose high speed image processing systems. In order to fabricate smart vision chips including photo detector compactly, we have proposed the application of three dimensional LSI technology for smart vision chips. Three dimensional technology has great potential to realize new neuromorphic systems inspired by not only the biological function but also the biological structure. In this paper, we describe our three dimensional LSI technology for neuromorphic circuits and the design of smart vision chips .

We describe a new multiport memory which is called Shared DRAM (SHDRAM) to solve bus-bottle neck problem in parallel processor system with shared memory. This SHDRAM has four ports. Therefore four processors can be directly connected to this memory without bus-bottle neck. The basic operation of SHDRAM is confirmed by computer simulation and measurement results.