Efficient resource allocation which aims to maximize the network utility under energy neural operation is well known as a key issue in energy harvesting wireless sensor networks (EHWSNs). However, as the energy resource is unstable in practical systems, it's challenging to tackle the uncertainty in harvested energy profile. Instead of designing sophisticated harvested energy prediction model, we directly make uncertainty involved in the resource allocation design. Considering the uncertainty of harvested energy profile, a flexible network utility optimization approach is proposed that can achieve high network utility and robustness against uncertain harvested energy. We firstly formulate the network utility maximization problem subject to energy constraints involving uncertainty. We then introduce a flexible uncertainty model to describe the harvested energy and transform the network utility maximization with uncertainties into a traditional optimization problem. Our experimental results demonstrate the proposed approach is able to provide flexible energy allocation and achieve robustness.

Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias (TSVs). All the dies in a 2.5D IC must be adequately tested for product qualification. However, due to the limited number of package pins, it is a major challenge to test 2.5D ICs using conventional methods. Moreover, due to higher integration levels, test-application time and test power consumption for 2.5D ICs are also increased compared to their 2D counterparts. Therefore, it is imperative to take these issues into account during 2.5D IC testing. In this article, we present an efficient multicast test architecture for targeting defects in dies, in which multiple dies can be tested simultaneously to reduce the test-application time under constraints on test power and fault coverage. We also propose a test scheduling and optimization technique that can be utilized with the multicast test architecture. By considering the trade-off between test-application time, test-power budget, and test quality, the proposed technique provides test schedules with minimum test-application time under constraints on power consumption and fault coverage. Compared to previous work, the proposed technique can reduce test-application time by up to 53.4 for benchmark designs while achieving higher fault coverage. Since the loss in fault coverage due to multicast testing is extremely small, we can use top-off patterns to achieve full fault coverage for the dies at negligible additional cost.

In interposer-based 2.5-D integrated circuits, the passive silicon interposer is the least expensive component in the chip. Thus, it is desirable to test the interposer before bonding to ensure that more expensive and defect-free dies are not stacked on a faulty interposer. We present an efficient method to locate defects in a passive interposer before stacking. The proposed test architecture uses e-fuses that can be programmed to connect or disconnect functional paths inside the interposer. The concept of die footprint is utilized for interconnect testing, and the overall assembly and test flow is described. Moreover, the concept of weighted critical area is defined and utilized to reduce test time. In order to fully determine the location of each e-fuse and the order of functional interconnects in a test path, we also present a test-path design algorithm. The proposed algorithm can generate all test paths for interconnect testing. We present HSPICE simulation results to demonstrate the effectiveness of the prebond test solution. Test-path designs are also presented to highlight the efficiency of the test-path design algorithm. The benefit of using weighted critical area is demonstrated using a commercial interposer from industry.

Interposer-based 2.5-D integrated circuits (ICs) enable high-density interconnects, but introduce new challenges for the testing of a system-on-chip (SoC) die on an interposer. This paper presents two efficient ExTest scheduling strategies that implements interconnect testing between tiles inside an SoC die while satisfying the practical constraint that the number of required test pins cannot exceed the number of available pins at the chip level. These strategies target two different ways in which SoC dies are wrapped in 2.5-D ICs. The first scheduling approach is aimed at an extremely large SoC in which the wrapper design requires concurrent testing of the interconnects driving the tile under test. The second scheduling approach is applicable to more general wrapper designs that provide more flexibility in terms of the manner in which these interconnects can be tested. In both test strategies, the tiles in the SoC die are divided into groups based on the manner in which they are interconnected. In order to minimize the test time, two optimization solutions are introduced. The first solution minimizes the number of input test pins, and the second solution minimizes the number of output test pins. In addition, two subgroup configuration methods are further proposed to generate subgroups inside each test group. To highlight the effectiveness of the proposed test strategies, we present scheduling and optimization results for two SoC dies for 2.5-D ICs currently in production.

Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias. This paper describes some of the major challenges related to testing of 2.5D ICs and presents some solutions to these problems. We first describe a test architecture using e-fuses for pre-bond interposer testing. We next present an efficient built-in self-test (BIST) technique that targets the dies and the interposer interconnects. Finally, we present a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs.

Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias (TSVs). All the dies in a 2.5D IC must be adequately tested for product qualification. However, due to the limited number of package pins, it is a a major challenge to test 2.5 ICs using conventional methods. Moreover, due to higher integration levels, test-application time and test power consumption for 2.5D ICs are also increased compared to their 2D counterparts. Therefore, it is imperative to take these issues into account during 2.5D IC testing. In this work, we present an efficient multicast test architecture for targeting defects in dies, in which multiple dies can be tested simultaneously to reduce the test-application time under constraints on test power and fault coverage. We also propose a test scheduling and optimization technique that can be utilized with the multicast test architecture. Compared to previous work, the proposed technique can reduce testapplication time by 53:4% for benchmark designs while achieving higher fault coverage.

Monolithic three-dimensional integrated circuits (M3D ICs) are being advocated as the next generation of 3D integration beyond 3D ICs based on through-silicon-vias. Testing of the bottom layer of an M3D IC is necessary to target defects arising from the layered manufacturing process. We present an efficient design-for-test (DfT) method for the bottom layer by isolating it from the top layer. A bypass structure based on e-fuses is proposed to connect pairs of inter-layer vias (ILVs). In order to minimize the wire length between paired ILVs, an ILV-pairing problem is formulated and then solved using a technique based on maximum-weighted bipartite matching. The independent ILVs, i.e., those that are not paired, are made controllable and observable using four different types of DfT structures. A cost-optimization problem is solved to minimize the DfT cost. We present ILV-pairing and cost-optimization results for designs based on the ITC'02 benchmarks as well as for an industry design. We also present HSpice simulation results to show that testing using e-fuses is feasible.

Three-dimensional (3D) integration using through-silicon vias (TSVs) promises higher integration levels in a single package, keeping pace with Moore's law. Despite the promise and benefits offered by 3D integration, testing remains a major obstacle that hinders its widespread adoption. This paper examines the hype, myths, and realities of 3D IC testing. We describe a number of testing and DfT challenges, and present some solutions being advocated for the challenges of “What to Test”, “How to Test”, and “When to Test”. Techniques highlighted in this paper include: (i) testing of the silicon interposer; (ii) pre-bond TSV testing; (iii) cost modeling and test-flow selection; (iv) a reconfigurable built-in self-test infrastructure.

Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias (TSVs). All the dies and the interposer in a 2.5D IC must be adequately tested for product qualification. This work provides solutions to new challenges related to testing of 2.5D ICs. We propose a test architecture using e-fuses for pre-bond interposer testing. We design a test architecture that is fully compatible with the IEEE 1149.1 standard and relies on an enhancement of the standard test access port (TAP) controller. We present an efficient built-in self-test (BIST) technique that targets the dies and the interposer interconnects. We next describe two efficient ExTest scheduling strategies that implement interconnect testing between tiles within a system on chip (SoC) die on the interposer. Finally, we present a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs.

We present a programmable method for shift-clock stagger assignment to reduce power supply noise during system-on-chip (SoC) testing. An SoC design is typically composed of several blocks and two neighboring blocks that share the same power rails should not be toggled at the same time during shift. Therefore, the proposed programmable method does not assign the same stagger value to neighboring blocks. The positions of all blocks are first analyzed and the shared boundary length between blocks is then calculated. Based on the position relationships between the blocks, a mathematical model is presented to derive optimal result for small-to-medium sized problems. For larger designs, a heuristic algorithm is proposed and evaluated. We present assignment results as well as power-analysis results and silicon data for industry designs to highlight the effectiveness of the proposed method.

Interposer-based 2.5D integrated circuits (ICs) enable high-density interconnects, but introduce new challenges for the testing of a system-on-chip (SoC) die on an interposer. This paper presents an efficient ExTest scheduling strategy that implements interconnect testing between tiles inside an SoC die while satisfying the practical constraint that the number of required test pins cannot exceed the number of available pins at the chip level. The tiles in the SoC are divided into groups based on the manner in which they are interconnected. In order to minimize the test time, two optimization solutions are introduced. The first solution minimizes the number of input test pins, and the second solution minimizes the number of output test pins. We present scheduling and optimization results for a “monster” die with 50 million flip-flops in a 2.5D IC, which is currently in production, to highlight the effectiveness of the proposed test strategy.

Interposer-based 2.5-D integrated circuits (ICs) are seen today as a first step toward the eventual industry adoption of 3-D ICs based on through-silicon vias (TSVs). The TSVs and the redistribution layer (RDL) in the silicon interposer, and micro-bumps in the assembled chip must be adequately tested for product qualification. We present an efficient interconnect-test solution that targets TSVs, RDL wires, and micro-bumps for shorts, opens, and delay faults. The proposed test technique is fully compatible with the IEEE 1149.1 Standard. To reduce test cost, we also present a test-path design and scheduling technique that minimizes a composite cost function based on test time and the design-for-test overhead in terms of additional TSVs and micro-bumps needed for test access. The locations of the dies on the interposer are taken into consideration in order to determine the order of dies in a single test path. We present simulation results to demonstrate the effectiveness of fault detection, and synthesis results to evaluate the hardware cost per die relative to the IEEE 1149.1 Standard. We also present test-path design and test-scheduling results to highlight the effectiveness of the optimization technique.

Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias (TSVs). All the dies and the interposer in a 2.5D IC must be adequately tested for product qualification. We present an efficient built-in self-test (BIST) architecture for targeting defects in dies and in the interposer interconnects. The proposed BIST architecture can also be used for fault diagnosis during interconnect testing. To reduce the overall test cost, we describe a test scheduling and optimization technique under power constraints. We present simulation results to validate the BIST architecture and demonstrate fault detection, synthesis results to evaluate the area overhead of the proposed BIST architecture, and test scheduling results to highlight the effectiveness of the optimization approach.

Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias (TSVs). All the dies and the interposer in a 2.5D IC must be adequately tested for product qualification. We present an efficient built-in self-test (BIST) architecture for targeting defects in dies and in the interposer interconnects. The proposed BIST architecture can also be used for fault diagnosis during interconnect testing. We present simulation results to validate the BIST architecture and demonstrate fault detection, synthesis results to evaluate the area overhead of the proposed BIST architecture, and fault coverage results to highlight the effectiveness of the proposed technique.

Interposer-based 2.5D integrated circuits (ICs) are seen today as a first step towards the eventual industry adoption of 3D ICs based on through-silicon vias (TSVs). The TSVs and the redistribution layer (RDL) in the silicon interposer, and micro-bumps in the assembled chip must be adequately tested for product qualification. We present an efficient interconnect-test solution that targets TSVs, RDL wires, and micro-bumps for shorts, opens, and delay faults. The proposed test technique is fully compatible with the IEEE 1149.1 Standard. To reduce test cost, we also present a test-path design and scheduling technique that minimizes a composite cost function based on test time and the design-for-test overhead in terms of additional TSVs and micro-bumps needed for test access. We present simulation results to demonstrate the effectiveness fault detection, and synthesis results to evaluate the hardware cost per die relative to 1149.1. We also present test-path design and test-scheduling results to highlight the effectiveness of the optimization technique.

2.5-D integration is emerging as the precursor to stacked 3-D ICs. Since the silicon interposer and micro-bumps in 2.5-D integration can suffer from fabrication and assembly defects, post-bond testing is necessary for product qualification. This paper proposes and evaluates an interposer test architecture based on extensions to the IEEE 1149.1 standard. The proposed method enables access to interconnects inside the interposer by probing on the C4 bumps. It provides an effective test method for opens, shorts, and interconnect delay defects in the interposer. Moreover, micro-bumps can be tested through test paths that include dies on the interposer. The proposed test technique is fully compatible with the IEEE 1149.1 architecture and can be controlled by the test-access port controller. We present HSPICE and ModelSim simulation results to demonstrate the effectiveness of fault detection. Simulation results show that a large range of defects can be detected, diagnosed, and characterized using the proposed approach. We also present synthesis results to evaluate the hardware cost per die relative to the IEEE 1149.1 standard. Synthesis results show that the cost of implementation of the architecture is negligible.

Recently proposed power-gating structures for intermediate power-off modes offer significant power saving benefits as they reduce the leakage power during short periods of inactivity. Even though they are very effective for reducing static power consumption, their reliable operation can be compromised by process variations and manufacturing defects. In this paper, we propose a signature analysis technique to efficiently test power-gating structures that provide intermediate power-off modes. Based on this technique, a methodology to repair catastrophic and parametric faults, and to tolerate process variations is presented. For testing and repairing multimode power switches, we propose a robust built-in self-test and built-in self-repair scheme that reduces test cost and obviates additional manufacturing steps for post-silicon repair. Simulation results highlight the low-cost and effectiveness of the proposed method for detecting, diagnosing, and repairing defects.

2.5D integration is emerging as a precursor to stacked 3D ICs. Since the silicon interposer and micro-bumps in 2.5D integration can suffer from fabrication and assembly defects, post-bond testing is necessary for product qualification. This paper proposes and evaluates an interposer test architecture based on extensions to the IEEE 1149.1 Std. The proposed method enables access to interconnects inside the interposer by probing on the C4 bumps. It provides an effective test method for opens, shorts, and interconnect delay fault in the interposer. Moreover, micro-bumps can be tested through test paths that include dies on the interposer. HSPICE simulation results show that a large range of defects can be detected, diagnosed, and characterized using the proposed approach.