Venkata R. Immaneni

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2ranked-venue papers
1as first author
0since 2021 · last 1993
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 100%

Topics — the 1 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
microprogramming
0.011993
Vertical Migration of Software Functions and Algorithms Using Enhanced Microsequencing · IEEE Trans. Computers 1993

Methods — techniques the papers use, named apart from their topics

microsequencing · 0.0compilation · 0.0
YearPublicationVenuePosition
1993 Vertical Migration of Software Functions and Algorithms Using Enhanced Microsequencing
abstract
A scheme for vertical migration of algorithms and functions with complex sequencing structure from software through firmware into microcoded VLSI structures is discussed. The expected benefits of migration are gains in speed, reliability, and stability. The scheme employs a migration model that is based on microcode modularity and is supported by a hardware microcontroller with enhanced sequencing capability. The basic idea is to capture, using effective compilation techniques, the explicit or implicit sequencing structure of a function. Migration is then effected by sequencing calls into a library of microcode modules of a target machine architecture. The modularity of the migration system is well suited for generating VLSI microcode. The experimental results from an environment consisting of several firmware development tools show substantial time performance improvements in comparison to software implementations. Comparisons to traditional migration approaches indicate that the proposed scheme is faster and requires less memory space for the migration of software algorithms into firmware.>
Christos A. Papachristou, Venkata R. Immaneni
IEEE Trans. Computers2
1990 Direct access test scheme-design of block and core cells for embedded ASICs
abstract
Intel requires the use of a direct-access test scheme in embedded-core or block-based ASIC (application-specific integrated-circuit) designs. This scheme provides for separate testing of individual block or core cells using proven test vectors. The authors discuss the design modifications for block cells with low pin counts, user application blocks, and large cores with high pin counts. The implementation and verification of the direct-access test scheme in a block- or core-based embedded ASIC design are also briefly described.>
Venkata R. Immaneni, Srinivas Raman
ITC1