This paper proposes a new framework for digital image processing; it relies on inexact computing to address some of the challenges associated with the discrete cosine transform (DCT) compression. The proposed framework has three levels of processing; the first level uses approximate DCT for image compressing to eliminate all computational intensive floating-point multiplications and executing the DCT processing by integer additions and in some cases logical right/left shifts. The second level further reduces the amount of data (from the first level) that need to be processed by filtering those frequencies that cannot be detected by human senses. Finally, to reduce power consumption and delay, the third level introduces circuit level inexact adders to compute the DCT. For assessment, a set of standardized images are compressed using the proposed three-level framework. Different figures of merits (such as energy consumption, delay, power-signal-to-noise-ratio, average-difference, and absolute-maximum-difference) are compared to existing compression methods; an error analysis is also pursued confirming the simulation results. Results show very good improvements in reduction for energy and delay, while maintaining acceptable accuracy levels for image processing applications.

For a parameterized family of homogeneous sliding mode based controllers under the influence of bounded perturbation, a strong Lyapunov function is presented for the first time. The family of controllers range from twisting algorithm, the linear PD control law, to the uniformly stable control law. The strict homogeneous Lyapunov function proposed here allows the estimation of the ultimate bound of convergence of the trajectories of the system, in finite-time, exponentially, or uniformly, by exploiting the homogeneity properties of the system, even in the case when it is affected by bounded non-vanishing persistent external perturbation.

In this paper a strong Lyapunov function is proposed, for the first time, for a parameterized family of homogeneous sliding mode based controllers. Indeed, from twisting algorithm, to the linear PD control law, to the uniformly stable control law, a general homogeneous family of control algorithms are considered. The strict locally Lipschitz homogeneous Lyapunov function allows the possibility to estimate an upper bound for the convergence time of the trajectories of the system to the equilibrium point, in finite-time, exponentially, or uniformly asymptotically, by exploiting the homogeneity properties of the system. Moreover, the introduction of Lyapunov function allows the analysis of the relationship between the control gains and its convergence time.

This paper presents a new method for diagnosing (detection and location) multiple faults in an application-dependent interconnect of a SRAM-based FPGA. For fault detection, the proposed technique retains the original interconnect configuration and modifies the function of the LUTs using the new LUT programming function 1-Bit Sum Function (1-BSF); in addition, it utilizes features such as branches in the nets as well as the primary (unused) IOs of the FPGAs. The proposed method detects all possible stuck-at and bridging faults of all cardinalities in a single configuration; fault detection requires$1 + {\rm log}_{2}k$test configurations for multiple stuck-at location and$2 + 2{\rm log}_{2}k$additional test configurations to locate more than one pair-wise bridging faults (where$k$denotes the maximum combinational depth of the FPGA circuit). Following detection, the locations of multiple faults are hierarchically identified using the walking-1 test set and an adaptive approach for the interconnect structure. Net ordering independence is accomplished by utilizing features such as the presence of paths of nets that are either disjoint or joint between the primary input and at least one primary output. As validated by simulation on benchmark circuits, the proposed method scales extremely well for different Virtex FPGA families; this results in a significant reduction in the number of configurations for diagnosing multiple faults.

This paper presents a new method for generating configurations for application-dependent testing of a SRAM-based FPGA interconnect. This method connects an activating input to multiple nets, thus generating activating test vectors for detecting stuck-at, open, and bridging faults. This arrangement permits a reduction in the number of redundant configurations, thus also achieving a reduction in test time for application-dependent testing at full fault coverage. As the underlying solution requires an exponential complexity, a heuristic algorithm that is polynomial and greedy in nature (based on sorting) is used for net selection in the configuration generation process. It is proved that this algorithm has an execution complexity of O(L3) (where L is the number of LUTs in the design). The proposed method requires at most log2(M + 2) configurations (where M denotes the number of activating inputs) as Walsh coding is employed. Moreover, it is scalable with respect to LUT inputs. Extensive logic-based simulation results are provided for ISCAS89 sequential benchmark designs implemented on Xilinx Virtex4 FPGAs; these results shows that the proposed method achieves a considerable reduction in the number of test configurations compared with methods found in the technical literature (on average, a reduction of 49.5 percent).

This paper presents a new method for locating multiple faults in an interconnect following application testing of an FPGA. This method utilizes conditions related to the interconnect structure and in particular, the presence of paths of nets that are either disjoint or joint between the primary input and at least one primary output. They yield to a rather adaptive approach by which faults are hierarchically located using the walking-1 test set. The proposed method is not dependent on net ordering and is capable to locate multiple stuck-at and pairwise bridging faults. This process requires 1+log2k test configurations for multiple stuck-at location and 2+2log2k additional test configurations to locate more than one pair-wise bridging faults (where k denotes the maximum combinational depth). As validated by simulation for benchmark circuits (implemented on the Xilinx Virtex4), the proposed method results in a significant reduction in the number of configurations.

This paper presents a new method for application-dependent testing of SRAM-based FPGA interconnects at run time. This method utilizes new features related to the function for the programming of the LUTs, the utilization (by logic activation/deactivation) of the nets in a interconnect configuration as well as the primary (unused) IOs of the FPGAs. A new LUT programming function is introduced, the proposed method retains the original interconnect configuration and modifies the function of the LUTs using the so-called 1-Bit Sum Function (1-BSF), the 1-BSF detects all possible stuck-at and bridging faults (of all cardinalities) by utilizing the all zeros' vector and a walking-1 test set. As validated by simulation for benchmark circuits (implemented on the Xilinx Virtex4), the proposed method results in a single test configuration with 100% coverage under the assumed fault model.