Since the redundancy analysis (RA) has been introduced for memory yield, many RA researches have been conducted. However, objective comparisons of them are difficult by the absence of real memory models with realistic fault distributions. This paper presents a fail memory configuration set for RA estimation, called as ITC'2020 RA Benchmarks. It enables objective estimations of RAs with respect to effectiveness and efficiency. The fail memory configuration set includes memory models which have various redundancy structures and a fault generation algorithm with fault distribution which can be criteria for objective comparisons of RA. Simulations for estimations and comparisons of RA researches including BIRA are progressed utilizing the fail memory configuration set.

A new 3-D fuse architecture is proposed to improve the yield of 3-D memories. Because the 2-D memories are stacked to form a 3-D memory, the repair status of the prebond is kept as the good status. However, if faults occur in the postbond on the same cells which were repaired in the prebond, they must be identified and repaired because they cannot be repaired by the previous methods. There is no research on the repair the same faulty cells which occur in the prebond and postbond yet. Therefore, the new 3-D fuse architecture is proposed to repair the faulty cells which occur in the prebond and postbond. The redundancies which repair the faulty cells in the prebond are invalidated. The faulty cells are repaired by other redundancies in the postbond by the proposed 3-D fuse architecture. Thus, the proposed technique can improve the yield of 3-D memories. The experimental results show that the proposed technique can achieve higher yields of 3-D memories because only the proposed technique can repair the same faulty cells occurring in the prebond and postbond, and verify the good repair status of the 3-D memories.

A new built-in self-repair (BISR) scheme is proposed for multiple embedded memories to find optimum point of the performance of BISR for multiple embedded memories. All memories are concurrently tested by the small dedicated built-in self-test to figure out the faulty memories, the number of faults, and irreparability. After all memories are tested, only faulty memories are serially tested and repaired by the shared built-in redundancy analysis according to the sizes of memories in descending order. Thus, the fast test and repair are performed with low area overhead. To accomplish an optimal repair rate and a fast analysis speed, an exhaustive search for all combinations of spare rows and columns is proposed based on the optimized fault collection. Experimental results show that the proposed BISR has the optimal repair rate because of the exhaustive search. The performance of the proposed BISR is located in the optimum point between the test and repair time, and the area overhead. For example, the proposed BISR requires 49.6% of the area and 1.3 times of the test and repair time in comparison with parallel BISR scheme for four memories (one 128 K, two 256 K, and one 512 K memories). Furthermore, the more there are memories, the more superior performance in terms of the test and repair time, and the area overhead is shown.

A 3-dimensional Built-In Self-Repair (3D BISR) scheme is proposed for 3-dimensional (3D) memories. The proposed 3D BISR scheme consists of two phases: a parallel test-repair phase, and a serial test-repair phase. After all memory dice are simultaneously tested, only the faulty memory dice are serially tested and repaired using one Built-In Redundancy Analysis (BIRA) module. Thus, it is a faster test-repair with low area overhead. The proposed BIRA algorithm with a post-share redundancy scheme performs exhaustive searches for all combinations of spare rows and columns. Experimental results show that the proposed 3D BISR is up to two times faster than the 3D serial test-serial repair BISR when seven 2048 × 2048 bit memory dice are stacked. The proposed 3D BISR requires 44.55% of the area in comparison to a 3D parallel test-parallel repair BISR for four stacked memory dice (one 128 K RAM, two 256 K RAMs, and 512 K RAM). The yield of 3D memories is the highest due to the exhaustive search BIRA algorithm with the post-share redundancy scheme as shown in various experimental results.

3-D-stacked memory using through-silicon-vias (TSVs) has emerged as a good alternative for overcoming the limitation of 2-D memory technology. Among many issues with 3-D-stacked memory, yield is one of the major challenges for mass production. This paper proposes a new fuse architecture and redundancy scheme to improve the yield of 3-D-stacked memories. The new fuse architecture is developed based on the fact that the unused redundancies in prebond repair cause the inefficiency. Therefore, the new fuse architecture provides a way to share redundancies in prebond and postbond repairs. There are two kinds of operation modes. One is an enable mode for collecting the used redundancy information. The other is a mask mode for obtaining faulty redundancy information using a short test algorithm. Using the new fuse architecture, a new redundancy scheme called the post-share scheme is developed to achieve optimal yield. The post-share scheme allocates the fixed number of spare rows and columns for each repair just like other schemes. However, only allocated redundancies are used in prebond repair, while both the redundancies allocated for postbond repair and unused redundancies in prebond repair can be used for postbond repair. Experimental results show that the post-share redundancy scheme significantly increases the final yield of 3-D-stacked memories and the increase of area overhead is small.

The test cost and yield improvement of embedded memories have become very important as memory capacity and density have grown. For embedded memories, built-in redundancy analysis (BIRA) is widely used to improve yield by replacing faulty cells with a 2-D redundancy architecture. However, the most important factor in BIRA is the reduction of hardware overhead while keeping optimal repair rate. Most BIRA approaches require extra hardware overhead in order to store and analyze faults in the memory. These approaches do not utilize spare memories during the redundancy analysis (RA) procedure. However, the proposed BIRA minimizes area overhead by utilizing a part of the spare memory as an address mapping table (AMT). Since storing the faulty memory addresses take most of the extra hardware overhead, the reduced logical addresses produced by the AMT are used to reduce the extra hardware overhead. In addition, the reduced addresses are stored in content-addressable memories (CAMs) and used in the RA procedure. The proposed BIRA can achieve an optimal repair rate by using an exhaustive search RA algorithm. The proposed RA algorithm compares the repair solution candidates with all the fault addresses stored in the proposed CAMs to guarantee an exhaustive search. The experimental results show that the proposed BIRA requires a smaller area overhead than that of the previous state-of-the-art BIRA with an optimal repair rate.

Three-dimensional (3-D) memories using through-silicon-vias (TSVs) as vertical buses across memory layers has regarded as one of 3-D integrated circuits (ICs) technology. The memory dies to stack together in a 3-D memory are selected by a die selection method. In order to improve yield of 3-D memories, redundancy sharing between inter-die using TSVs is an effective strategy. With the redundancy sharing strategy, the bad memory dies can become good 3-D memories through matching the good memory dies. To support die selection and matching efficiently, a novel redundancy analysis (RA) algorithm, which considers various repair solutions, is proposed. Because the repair solutions can be various, the proposed die selection and matching is performed with two stages; general die selection and matching method in the first stage and re-matched remained memory dies, after the first stage, applying other repair solutions in the second stage. Thus, the proposed die selection and matching algorithm using the proposed RA algorithm can improve yield of 3-D memories. The experimental results show that the proposed die selection and matching method can achieve higher yield of 3-D memories than that of the previous state-of-the-art the die selection and matching methods.

Faulty cell repair with redundancy can improve memory yield. In particular, built-in redundancy analysis (BIRA) is widely used to enhance the yield of embedded memories. We propose an efficient BIRA algorithm to achieve the optimal repair rate with a very short analysis time and low hardware cost. The proposed algorithm can significantly reduce the number of backtracks in the exhaustive search algorithm: it uses early termination based on the number of orthogonal faulty cells and fault classification in fault collection. Experimental results show that the proposed BIRA methodology can achieve optimal repair rate with low hardware overhead and short analysis time, as compared to previous BIRA methods.