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Juan Luis Jerez

dblp:12/9240 · DBLP profile ↗
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4ranked-venue papers
4as first author
0since 2021 · last 2015
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 4 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Processor architecture and microarchitecture · 37% Reconfigurable computing and FPGAs · 21% Hardware accelerators and domain-specific architectures · 21%
Theoretical computer science
2 papers
Algorithms and data structures · 92% Mathematical optimization · 8%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › computer arithmetic
fixed-point arithmetic
0.212015
A Low Complexity Scaling Method for the Lanczos Kernel in Fixed-Point Arithmetic · IEEE Trans. Computers 2015
Algorithms and data structures › numerical linear algebra
eigenvalue computation
0.212015
A Low Complexity Scaling Method for the Lanczos Kernel in Fixed-Point Arithmetic · IEEE Trans. Computers 2015
Algorithms and data structures
linear algebra
0.212015
A Low Complexity Scaling Method for the Lanczos Kernel in Fixed-Point Arithmetic · IEEE Trans. Computers 2015
Reconfigurable computing and FPGAs
FPGA implementation
0.112011
An FPGA implementation of a sparse quadratic programming solver for constrained predictive control · FPGA 2011
Embedded and real-time systems › control systems
model predictive control
0.112011
An FPGA implementation of a sparse quadratic programming solver for constrained predictive control · FPGA 2011
Hardware accelerators and domain-specific architectures
quadratic programming solver
0.112011
An FPGA implementation of a sparse quadratic programming solver for constrained predictive control · FPGA 2011
Mathematical optimization › numerical computation › numerical optimization › second-order methods
interior point methods
0.012011
An FPGA implementation of a sparse quadratic programming solver for constrained predictive control · FPGA 2011

Methods — techniques the papers use, named apart from their topics

scaling procedure · 0.4analytical bounds · 0.4sparsity exploitation · 0.2floating-point · 0.2interior-point method · 0.1interior point method · 0.1
YearPublicationVenuePosition
2015 A Low Complexity Scaling Method for the Lanczos Kernel in Fixed-Point Arithmetic
abstract
We consider the problem of enabling fixed-point implementation of linear algebra kernels on low-cost embedded systems, as well as motivating more efficient computational architectures for scientific applications. Fixed-point arithmetic presents additional design challenges compared to floating-point arithmetic, such as having to bound peak values of variables and control their dynamic ranges. Algorithms for solving linear equations or finding eigenvalues are typically nonlinear and iterative, making solving these design challenges a nontrivial task. For these types of algorithms, the bounding problem cannot be automated by current tools. We focus on the Lanczos iteration, the heart of well-known methods such as conjugate gradient and minimum residual. We show how one can modify the algorithm with a low-complexity scaling procedure to allow us to apply standard linear algebra to derive tight analytical bounds on all variables of the process, regardless of the properties of the original matrix. It is shown that the numerical behavior of fixed-point implementations of the modified problem can be chosen to be at least as good as a floating-point implementation, if necessary. The approach is evaluated on field-programmable gate array (FPGA) platforms, highlighting orders of magnitude potential performance and efficiency improvements by moving form floating-point to fixed-point computation.
Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan
IEEE Trans. Computers1
2012 Fixed Point Lanczos: Sustaining TFLOP-equivalent Performance in FPGAs for Scientific Computing
abstract
We consider the problem of enabling fixed-point implementations of linear algebra kernels to match the strengths of the field-programmable gate array (FPGA). Algorithms for solving linear equations, finding eigen values or finding singular values are typically nonlinear and recursive making the problem of establishing analytical bounds on variable dynamic range non-trivial. Current approaches fail to provide tight bounds for this type of algorithms. We use as a case study one of the most important kernels in scientific computing, the Lanczos iteration, which lies at the heart of well known methods such as conjugate gradient and minimum residual, and we show how we can modify the algorithm to allow us to apply standard linear algebra analysis to prove tight analytical bounds on all variables of the process, regardless of the properties of the original matrix. It is shown that the numerical behaviour of fixed-point implementations of the modified problem can be chosen to be at least as good as a double precision floating point implementation. Using this approach it is possible to get sustained FPGA performance very close to the peak general-purpose graphics processing unit (GPGPU) performance in FPGAs of comparable size when solving a single problem. If there are several independent problems to solve simultaneously it is possible to exceed the peak floating-point performance of a GPGPU, obtaining approximately 1, 2 or 4 TFLOPs for error tolerances of 10-7, 10-5and 10-3, respectively, in a large Virtex 7 FPGA.
Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan
FCCM1
2011 An FPGA implementation of a sparse quadratic programming solver for constrained predictive control
abstract
Model predictive control (MPC) is an advanced industrial control technique that relies on the solution of a quadratic programming (QP) problem at every sampling instant to determine the input action required to control the current and future behaviour of a physical system. Its ability in handling large multiple input multiple output (MIMO) systems with physical constraints has led to very successful applications in slow processes, where there is sufficient time for solving the optimization problem between sampling instants. The application of MPC to faster systems, which adds the requirement of greater sampling frequencies, relies on new ways of finding faster solutions to QP problems. Field-programmable gate arrays (FPGAs) are specially well suited for this application due to the large amount of computation for a small amount of I/O. In addition, unlike a software implementation, an FPGA can provide the precise timing guarantees required for interfacing the controller to the physical system. We present a high-throughput floating-point FPGA implementation that exploits the parallelism inherent in interior-point optimization methods. It is shown that by considering that the QPs come from a control formulation, it is possible to make heavy use of the sparsity in the problem to save computations and reduce memory requirements by 75%. The implementation yields a 6.5x improvement in latency and a 51x improvement in throughput for large problems over a software implementation running on a general purpose microprocessor.
Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan
FPGA1
2010 FPGA implementation of an interior point solver for linear model predictive control
abstract
Automatic control, the process of measuring, computing, and applying an input to control the behaviour of a physical system, is ubiquitous in engineering and industry. Model predictive control (MPC) is an advanced control technology that has been very successful in the chemical process industries due to its ability to handle large multiple input multiple output (MIMO) systems with physical constraints. It has recently been proposed to be applied to higher bandwidth systems, which add the requirement of greater sampling frequencies. The main hurdle is the need to solve a computationally intensive quadratic programming (QP) problem in real-time. In this paper we address the need for acceleration by proposing a highly efficient floating-point field-programmable gate array (FPGA) implementation that exploits the parallelism opportunities offered by interior-point optimization methods. The approach yields a 5x improvement in latency and a 40x improvement in throughput for large problems over a software implementation. This work builds on a previous FPGA implementation of an iterative linear solver, an operation at the heart of the interior-point method.
Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan
FPT1