Digital predistortion (DPD) is a widely used technique for enhancing signal quality in modern radio frequency (RF) power amplifiers (PAs). However, the strong performance of deep neural network (DNN)-based DPD models is often offset by their prohibitive computational complexity, which limits their practical deployment in wideband systems. This paper presents an attention-sparse gated recurrent unit (ATSGRU)—a novel neural architecture designed for computationally efficient wideband DPD in quadrature digital PAs (DPAs). The ATSGRU integrates the attention mechanism that evaluates the temporal relevance of input features and prunes redundant components, thereby simplifying the model structure and reducing computational load. The proposed method is validated on a custom 28-nm CMOS DPA chip. Experimental results demonstrate that the proposed ATSGRU achieves superior linearization with a favorable balance between accuracy and complexity compared with the state-of-the-art (SOTA) DPD model, reducing multiply-accumulate (MAC) operations by 54% while maintaining comparable performance. These results highlight its strong potential for efficient and scalable wideband DPD applications.

For the first time, this paper presents an unsupervised learning residual long short-term memory (ULR_LSTM) neural network to develop a digital predistortion (DPD) method for the linearization of digital power amplifiers (DPAs). Our method eliminates the need for iterative learning control (ILC) to obtain the ideal input of the DPA required by state-of-the-arts (SOTAs), which leads to high computational complexity and extensive training time. We perform behavioral modeling of the DPA using the R_LSTM network. After determining the optimal behavioral model architecture, the corresponding DPD model is obtained through an inverse training process. A 15-bit transformer-based quadrature DPA chip incorporating Class-G and IQ-cell-sharing techniques was implemented in a 28nm CMOS process to validate our proposed method. Experimental results demonstrate outstanding linearization performance comparing to prior arts, achieving an error vector magnitude (EVM) of -40.4dB for the 802.11ax 40MHz 64QAM signal.

This paper presents a modified vector combination (MVC) model to analyze the nonlinearity behavior in the quadrature switched-capacitor power amplifier (SCPA), which improves model accuracy while reducing the number of recorded points and iterations compared to the two-dimensional (2-D) LUT-based model. To analyze the nonlinearity caused by efficiency enhancement techniques, high-order Taylor series are applied to meet the model accuracy requirement. Moreover, a two-stage process with MVC and general memory polynomial (GMP) digital predistortion (DPD) is introduced to calibrate the static nonlinearity and memory effect, respectively. In the measurement, a 15-bit transformer-based quadrature SCPA chip with Class-G and IQ-cell-sharing techniques is implemented in 28nm CMOS and employed to verify the effectiveness of the MVC and two-stage DPD methods. For the 802.11ax 40MHz 64QAM signal at 2.4GHz, this chip achieves up to −40.9dB error vector magnitude (EVM) floor and significant EVM improvement even at deep power back-offs after the DPD.

In this paper, a novel two-stage digital predistortion method for quadrature digital power amplifiers (DPAs) is proposed. Digital transmitter architectures have advantages of compact die size owing to advanced CMOS process techniques, reconfigurability, and the usage of highly efficient switching-mode power amplifiers. However, the fluctuation of conductance resistance and interaction between in-phase and quadrature paths in quadrature DPAs complicates the parameters extraction process of the behavior model of power amplifiers, which necessitates the 2-D lookup table (2D-LUT) for compensation. A 2-D LUT is derived from the optimal predistortion input signal based on iterative learning control (ILC), which is aimed to calibrate the static nonlinearities. For wide bandwidth scenarios, the memory effect has to be taken into consideration which is neglected in the conventional 2D-LUT method. A general memory polynomial model is added to the whole system to fix the dynamic effect subsequently. Both the error vector magnitude (EVM) and normalized mean square error (NMSE) are used to evaluate the proposed two-stage predistortion method, which demonstrates EVMs of -32.46dB and -33.05dB for 802.11ax Wi-Fi 20MHz MCS9 and 40MHz MCS9 signals, respectively.

A 4.8-mm20.1-6.0-GHz dual-path software-defined radio transmitter supporting intraband carrier aggregation (CA) in 65-nm CMOS is presented. A simple approach is proposed to support intraband CA signals with only one I-Q baseband path. By utilizing the power-scalable and feedforward compensation techniques, the power of the wideband analog baseband is minimized. The transmitter consists of a high gain-range main path and a low-power subpath to cooperatively cover different standards over 0.1-6.0 GHz with more flexibility. The reconfigurable power amplifier (PA) driver achieves wideband frequency coverage with efficiency-enhanced on-chip transformers and improved switched-capacitor arrays. This transmitter achieves <;-50-dBc image rejection ratio and <;-40-dBc local oscillating signal leakage after the calibration. System verifications have demonstrated -31/- 51-dBc ACLR1/ACLR2 (adjacent channel leakage ratio) at 3-dBm output power for 2.3-GHz LTE20 in the main path and 1.7% error vector magnitude (EVM) at 1.5-dBm output for 1.8-GHz WCDMA in the subpath. Both paths enable SAW-less FDD operations with -153 or -156 dBc/Hz carrier-to-noise ratio at 200-MHz frequency offset. Finally, the dual CA signals with 55-MHz frequency spacing are verified, showing the EVM of 1.2% and 0.8%, respectively, and exhibiting the intraband CA capability.