This paper revisits the identity detection problem under the current grant-free protocol in massive machine-type communications (mMTC) by asking the following question: for stable identity detection performance, is it enough to permit active devices to transmit preambles without any handshaking with the base station (BS)? Specifically, in the current grant-free protocol, the BS blindly allocates a fixed length of preamble to devices for identity detection as it lacks the prior information on the number of active devices K. However, in practice, K varies dynamically over time, resulting in degraded identity detection performance especially when K is large. Consequently, the current grant-free protocol fails to ensure stable identity detection performance. To address this issue, we propose a two-stage communication protocol which consists of estimation of K in Phase I and detection of identities of active devices in Phase II. The preamble length for identity detection in Phase II is dynamically allocated based on the estimated K in Phase I through a table lookup manner such that the identity detection performance could always be better than a predefined threshold. In addition, we design an algorithm for estimating K in Phase I, and exploit the estimated K to reduce the computational complexity of the identity detector in Phase II. Numerical results demonstrate the effectiveness of the proposed two-stage communication protocol and algorithms.

The fifth version of the Reduced Instruction Set Computer (RISC-V) is a popular instruction set architecture (ISA) featured for low energy consumption. Currently, a growing number of industrial applications are based on RISC-V platforms, especially Internet of Things (IoT) devices. Those applications pursue low power and just sufficient computing capacity. However, low power consumption shall not be directly regarded as weak in computation. Recent advancement in RISC- V shows the potential for building a computing platform capable of handling tasks requiring considerable computing power. Traditional financial computing platforms are generally based on Complex Instruction Set Computers (CISC), like x86 platforms. As green computing is sweeping, it is meaningful to handle financial computing tasks with less energy consumption. To explore the potential of RISC- V in financial computing, we set up a typical financial computing task - American option implied volatility calculation, and examine the performance and power consumption of x86 and RISC-V platforms. The result shows that the RISC-V CPU is sufficient for some financial computing scenarios considering actual requirements. A heterogeneous computing system composed of x86 and RISC-V platforms could significantly improve energy efficiency.

Summarising from the Web could be formed as a problem of multi-document Summarisaiton (MDS) from multiple sources. In contrast to the current MDS problem that involves working on benchmark datasets which provide well clustered set of documents, we envisage to build a pipeline for content Summarisaiton from the Web, but narrow down to the Social Internet of Things (SIoT) paradigm, starting at data collection from the IoT objects, then applying natural language processing techniques for grouping and summarising the data, to distributing summaries back to the IoT objects. In this paper, we present our simulation tool, SimSumIoT, that simulates the process of data sharing, receiving, clustering, and Summarisaiton. A Web-based interface is developed for this purpose allowing users to visualize the process through a set of interactions. The Web interface is accessible via http://simsumlot.tk.

In this article, we present a graphical Computer-Aided Design (CAD) environment for the design, analysis, and layout of Carbon NanoTube (CNT) Field-Effect Transistor (CNFET) circuits. This work is motivated by the fact that such a tool currently does not exist in the public domain for researchers. Our tool has been integrated within Electric a very powerful, yet free CAD system for custom design of Integrated Circuits (ICs). The tool supports CNFET schematic and layout entry, rule checking, and HSpice/VerilogA netlist generation. We provide users with a customizable CNFET technology library with the ability to specify λ-based design rules. We showcase the capabilities of our tool by demonstrating the design of a large CNFET standard cell and components library. Meanwhile, HSPICE simulations also have been presented for cell library characterization. We hope that the availability of this tool will invigorate the CAD community to explore novel ideas in CNFET circuit design.