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Sam White

dblp:121/1956 · DBLP profile ↗
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4ranked-venue papers
1as first author
1since 2021 · last 2022
0000-0002-6019-8763ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Performance modeling and evaluation · 67% Interconnection networks and networks-on-chip · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Performance modeling and evaluation › simulation › communication system simulation
network simulation
0.212016
Evaluating HPC networks via simulation of parallel workloads · SC 2016
Performance modeling and evaluation › simulation › communication system simulation
packet-level simulation
0.212016
Evaluating HPC networks via simulation of parallel workloads · SC 2016
Interconnection networks and networks-on-chip
topology comparison
0.212016
Evaluating HPC networks via simulation of parallel workloads · SC 2016

Methods — techniques the papers use, named apart from their topics

tracer simulator · 0.2proxy applications · 0.2
YearPublicationVenuePosition
2022 Accelerating communication for parallel programming models on GPU systems
Zane Fink, Sam White, Nitin Bhat, David F. Richards, Laxmikant V. Kalé
Parallel Comput.3
2020 Optimizing point-to-point communication between adaptive MPI endpoints in shared memory
abstract
Summary Adaptive MPI is an implementation of the MPI standard that supports the virtualization of ranks as user‐level threads, rather than OS processes. In this work, we optimize the communication performance of AMPI based on the locality of the endpoints communicating within a cluster of SMP nodes. We differentiate between point‐to‐point messages with both endpoints co‐located on the same execution unit and point‐to‐point messages with both endpoints residing in the same process but not on the same execution unit. We demonstrate how the messaging semantics of Charm++ enable and hinder AMPI's implementation in different ways, and we motivate extensions to Charm++ to address the limitations. Using the OSU micro‐benchmark suite, we show that our locality‐aware design offers lower latency, higher bandwidth, and reduced memory footprint for applications.
Sam White, Laxmikant V. Kalé
Concurr. Comput. Pract. Exp.1
2018 Multi-Level Load Balancing with an Integrated Runtime Approach
abstract
The recent trend of increasing numbers of cores per chip has resulted in vast amounts of on-node parallelism. These high core counts result in hardware variability that introduces imbalance. Applications are also becoming more complex, re-sulting in dynamic load imbalance. Load imbalance of any kind can result in loss of performance and system utilization. We address the challenge of handling both transient and persistent load imbalances while maintaining locality with low overhead. In this paper, we propose an integrated runtime system that combines the Charm++ distributed programming model with concurrent tasks to mitigate load imbalances within and across shared memory address spaces. It utilizes a periodic assignment of work to cores based on load measurement, in combination with user created tasks to handle load imbalance. We integrate OpenMP with Charm++ to enable creation of potential tasks via OpenMP's parallel loop construct. This is also available to MPI applications through the Adaptive MPI implementation. We demonstrate the benefits of our work on three applications. We show improvements of Lassen by 29.6% on Cori and 46.5% on Theta. We also demonstrate the benefits on a Charm++ application, ChaNGa by 25.7% on Theta, as well as an MPI proxy application, Kripke, using Adaptive MPI.
Seonmyeong Bak, Harshitha Menon, Sam White, Matthias Diener, Laxmikant V. Kalé
CCGrid3
2016 Evaluating HPC networks via simulation of parallel workloads
abstract
This paper presents an evaluation and comparison of three topologies that are popular for building interconnection networks in large-scale supercomputers: torus, fat-tree, and dragonfly. To perform this evaluation, we propose a comprehensive methodology and present a scalable packet-level network simulator, TraceR. Our methodology includes design of prototype systems that are being evaluated, use of proxy applications to determine computation and communication load, simulating individual proxy applications and multi-job workloads, and computing aggregated performance metrics. Using the proposed methodology, prototype systems based on torus, fat-tree, and dragonfly networks with up to 730K endpoints (MPI processes) executed on 46K nodes are compared in the context of multi-job workloads from capability and capacity systems. For the 180 Petaflop/s prototype systems simulated in this paper, we show that different topologies are superior in different scenarios, i.e. there is no single best topology, and the characteristics of parallel workloads determine the optimal choice.
Abhinav Bhatele, Sam White, Todd Gamblin, Laxmikant V. Kalé
SC3