Cryptographic wallets play a vital role in securing digital assets within blockchain networks by managing private keys that authorize secure transactions. However, side channel analysis (SCA) attacks have become a serious threat, enabling attackers to extract sensitive information by exploiting algorithmic weaknesses in microcontroller-based wallets, resulting in the loss of millions of dollars in digital assets. In hierarchically deterministic (HD) systems, the compromise of a single primary key can endanger all subsequent child keys, while the use of independent keys for each account introduces complexity and challenges in key management. This work presents HardVault, a field programmable gate array (FPGA)-based cryptocurrency wallet that supports both Bitcoin and Ethereum. HardVault introduces the first hardware wallet architecture that implements both non-deterministic (ND) and HD key generation modes directly in hardware, giving users the flexibility to choose either approach based on their security and usability needs. By leveraging constant-time operations and hardware-enforced private-key isolation, the design significantly improves resilience to SCA attacks. In addition, the architecture prioritizes resource efficiency to minimize area usage without compromising security, making it well-suited for compact, portable hardware wallet applications. Implementation on a ZCU104 FPGA shows that HardVault uses only 27% of available look-up tables (LUTs). Compared to the Trezor One cryptocurrency (crypto) wallet, the proposed implementation achieves$9\times $higher energy efficiency,$8\times $lower latency, and$7\times $higher throughput.

Ethereum leverages smart contracts (SCs) to power decentralized applications (dApps), with execution handled by the Ethereum virtual machine (EVM) within an Ethereum client. Other blockchain platforms, including Avalanche, Polkadot, Aurora, and Cardano, have also adopted the EVM. However, the performance of the EVM is often constrained by the limitations of general-purpose processors, a challenge that has been explored in the literature. This work aims to further address the limitation by proposing EVMx, a dedicated single-core SC execution engine implemented on a field programmable gate array (FPGA). EVMx follows a processor-like architecture inspired by the RISC philosophy. By exploiting the parallelism and high-speed processing capabilities of FPGA hardware, EVMx achieves a 61% to 99% reduction in execution time for commonly used operation codes compared to traditional central processing unit (CPU)-based environments. Furthermore, EVMx executes entire Ethereum blocks with a percentage reduction in execution time between 6% and 56% against comparable FPGA implementations and 98% to 99% compared to CPU-based EVMs in the literature. These results demonstrate the potential of EVMx to significantly accelerate SC execution and enhance the performance of EVM-compatible blockchains.

Ethereum blockchain uses smart contracts (SCs) to implement decentralized applications (dApps). SCs are executed by the Ethereum virtual machine (EVM) running within an Ethereum client. Moreover, the EVM has been widely adopted by other blockchain platforms, including Solana, Cardano, Avalanche, Polkadot, and more. However, the EVM performance is limited by the constraints of the general-purpose computer it operates on. This work proposes offloading SC execution onto a dedicated hardware-based EVM. Specifically, EVMx is an FPGA-based SC execution engine that benefits from the inherent parallelism and high-speed processing capabilities of a hardware architecture. Synthesis results demonstrate a reduction in execution time of 72% to 99% for commonly used operation codes compared to CPU-based SC execution environments. Moreover, the execution time of Ethereum blocks on EVMx is up to 6 ×faster compared to analogous works in the literature. These results highlight the potential of the proposed architecture to accelerate SC execution and enhance the performance of EVM-compatible blockchains.

In this paper, two decoding algorithms based on Successive-Cancellation (SC) are proposed to improve the error-correction performance of cyclic redundancy check (CRC)-aided polar codes while aiming for a low-complexity implementation. Comparisons with Dynamic SC Flip (DSCF) and SC Perturbation (SCP) are carried out since the proposed DSCF and Perturbation (DSCFP) and Perturbed DSCF (PDSCF) algorithms combine both methods. The analysis includes comparisons with several code lengths$N$and various number of decoding attempts$T_{max}$. For$N=1024$and the coding rate$R= 1/2$, the DSCF and the SCP algorithms with$T_{\max}= 17$are bested by approximately 0.1 dB at block-error rate (BLER) of 0.001. At BLER = 10−6and for$T_{max}= 64$, the gain is of 0.375 dB and > 0.5 dB with respect to DSCF and SCP, respectively. At high signal-to-noise ratio, the average computational complexity of the proposed algorithms is virtually equivalent to that of SC.

Automorphism Ensemble (AE) decoding has recently drawn attention as a possible alternative to list decoding of polar codes. In this letter, we investigate the distribution of Partially-Symmetric Reed-Muller (PS-RM) codes, a family of polar codes yielding good performances under AE decoding. We prove the existence of these codes for almost all code dimensions for code lengths N ≤ 256. Moreover, we analyze the absorption group of this family of codes under SC decoding, proving that valuable permutations in AE decoding always exist. Finally, we experimentally show that PS-RM codes can outperform state-of-the-art polar-code-construction algorithms in terms of error-correction performance for short code lengths, while reducing decoding latency.

Polar codes are a class of error-correcting codes that provably achieve the capacity of practical channels. The successive-cancellation flip (SCF) decoder is a low-complexity decoder that was proposed to improve the performance of the successive-cancellation (SC) decoder as an alternative to the high-complexity successive-cancellation list (SCL) decoder. The SCF decoder improves the error-correction performance of the SC decoder, but the variable execution time and the high worst-case execution time pose a challenge for the realization of receivers with fixed-time algorithms. The dynamic SCF (DSCF) variation of the SCF decoder further improves the error-correction performance but the challenge of decoding delay remains. In this work, we propose a simplified restart mechanism (SRM) that reduces the execution time of SCF and DSCF decoders through conditional restart of the additional trials from the second half of the codeword. We show that the proposed mechanism is able to improve the execution time characteristics of SCF and DSCF decoders while providing identical error-correction performance. For a DSCF decoder that can flip up to 3 simultaneous bits per decoding trial, the average execution time, the average additional execution time and the execution-time variance are reduced by approximately 31%, 37% and 57%, respectively. For this setup, the mechanism requires approximately 3.9% additional memory.

Lyra2REv2 is a hashing algorithm that consists of a chain of individual hashing algorithms and it is used as a proof-of-work function in several cryptocurrencies that aim to be ASIC-resistant. The most crucial hashing algorithm in the Lyra2REv2 chain is a specific instance of the general Lyra2 algorithm. In this work we present the first FPGA implementation of the aforementioned instance of Lyra2 and we explain how several properties of the algorithm can be exploited in order to optimize the design.

Successive-cancellation list (SCL) decoding is an algorithm that provides very good error-correction performance for polar codes. However, its hardware implementation requires a large amount of memory, mainly to store intermediate results. In this paper, a partitioned SCL algorithm is proposed to reduce the large memory requirements of the conventional SCL algorithm. The decoder tree is broken into partitions that are decoded separately. We show that with careful selection of list sizes and number of partitions, the proposed algorithm can outperform conventional SCL while requiring less memory.

Polar codes are an exciting new class of error correcting codes that achieve the symmetric capacity of memoryless channels. Many decoding algorithms were developed and implemented, addressing various application requirements: from error-correction performance rivaling that of LDPC codes to very high throughput or low-complexity decoders. In this work, we review the state of the art in polar decoders implementing the successive-cancellation, belief propagation, and list decoding algorithms, illustrating their advantages.

Polar codes asymptotically achieve the symmetric capacity of memoryless channels, yet their error-correcting performance under successive-cancellation (SC) decoding for short and moderate length codes is worse than that of other modern codes such as low-density parity-check (LDPC) codes. Of the many methods to improve the error-correction performance of polar codes, list decoding yields the best results, especially when the polar code is concatenated with a cyclic redundancy check (CRC). List decoding involves exploring several decoding paths with SC decoding, and therefore tends to be slower than SC decoding itself, by an order of magnitude in practical implementations. In this paper, we present a new algorithm based on unrolling the decoding tree of the code that improves the speed of list decoding by an order of magnitude when implemented in software. Furthermore, we show that for software-defined radio applications, our proposed algorithm is faster than the fastest software implementations of LDPC decoders in the literature while offering comparable error-correction performance at similar or shorter code lengths.

Conventional differential chaos-shift-keying systems (DCSK) are not the most suitable for supporting continuous-mobility scenarios. Therefore, in this paper an improved continuous-mobility differential chaos-shift-keying system (CM-DCSK) is presented that provides greater agility and improved performance in fast fading channels without accurate channel estimation while still being simple compared to a conventional DCSK system. A new DCSK frame signal is designed to reach this goal. In our new frame design, each reference sample is followed by a data carrier sample. This modification of the system design reduces the hardware complexity of DCSK because it requires a shorter wideband delay line and significantly improves the performance over fast fading channels while keeping the non-coherent nature of the transmission system. Once the design is explained, the bit error rate performance is computed over a multipath fast fading channel and compared to the conventional DCSK system. Simulation results confirm the advantages of this new noncoherent spread-spectrum design that can support mobility.

In this paper, we present hardware and software implementations of flexible polar systematic encoders and decoders. The proposed implementations operate on polar codes of any length less than a maximum and of any rate. We describe the low-complexity, highly parallel, and flexible systematic-encoding algorithm that we use and prove its correctness. Our hardware implementation results show that the overhead of adding code rate and length flexibility is little, and the impact on operation latency minor compared with code-specific versions. Finally, the flexible software encoder and decoder implementations are also shown to be able to maintain high throughput and low latency.

Among error-correcting codes, polar codes are the first to provably achieve channel capacity with an explicit construction. In this work, we present software implementations of a polar decoder that leverage the capabilities of modern general-purpose processors to achieve an information throughput in excess of 200 Mbps, a throughput well suited for software-defined-radio applications. We also show that, for a similar error-correction performance, the throughput of polar decoders both surpasses that of LDPC decoders targeting general-purpose processors and is competitive with that of state-of-the-art software LDPC decoders running on graphic processing units.

This work presents another look at an analog network coding scheme for multi-user spread-spectrum communication systems. Our proposed system combines coding and cooperation between a relay and users to boost the throughput and to exploit interference. To this end, each pair of users, A and B, that communicate with each other via a relay R shares the same spreading code. The relay has two roles, it synchronizes network transmissions and it broadcasts the combined signals received from users. From user B's point of view, the signal is decoded, and then, the data transmitted by user A is recovered by subtracting user B's own data. We derive the analytical performance of this system for an additive white Gaussian noise channel with the presence of multi-user interference, and we confirm its accuracy by simulation.

Polar codes provably achieve the symmetric capacity of a memoryless channel while having an explicit construction. The adoption of polar codes however, has been hampered by the low throughput of their decoding algorithm. This work aims to increase the throughput of polar decoding hardware by an order of magnitude relative to successive-cancellation decoders and is more than 8 times faster than the current fastest polar decoder. We present an algorithm, architecture, and FPGA implementation of a flexible, gigabit-per-second polar decoder.

In this paper, implementation of discrete-time chaotic generators widely used in digital communications is studied and evaluated. The study focuses on power consumption, resource usage, and maximum execution frequency of implementations for two common Field Programmable Gate Arrays (FPGAs). While the Bernoulli map ranks first in all three aspects, results show significant ranking differences among the other chaotic generators. Results were obtained by first implementing the chaotic generators in a high level register to transistor level description language and then using tools from FPGA manufacturers to obtain the resource usage as well as estimate the other desired characteristics.